ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 210
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ST72361AR9-Auto
Manufacturer Part Number
ST72361AR9-Auto
Description
8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
Manufacturer
STMicroelectronics
Datasheet
1.ST72361AR9-AUTO.pdf
(279 pages)
Specifications of ST72361AR9-Auto
Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
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LINSCI serial communication interface (LIN master only)
Note:
Note:
16.8.5
210/279
Bit 1 = CPHA Clock Phase.
This bit allows the user to select the phase of the clock output on the SCLK pin. It works in
conjunction with the CPOL bit to produce the desired clock/data relationship (see
and
Bit 0 = LBCL Last bit clock pulse.
This bit allows the user to select whether the clock pulse associated with the last data bit
transmitted (MSB) has to be output on the SCLK pin.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected
by the M bit in the SCICR1 register.
Table 76.
These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
Data register (SCIDR)
Read/ write
Reset value: Undefined
Contains the received or transmitted data character, depending on whether it is read from or
written to.
The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
8 bit
9 bit
Data format
DR7
Figure
0: SCLK clock line activated in middle of data bit.
1: SCLK clock line activated at beginning of data bit.
0: the clock pulse of the last data bit is not output to the SCLK pin.
1: the clock pulse of the last data bit is output to the SCLK pin.
7
93)
SCI clock on SCLK pin
DR6
Figure
Figure
88).
88).
M bit
0
1
DR5
Doc ID 12468 Rev 3
0
1
0
1
DR4
LBCL bit
DR3
7
8
8
9
Number of clock pulses on SCLK
DR2
DR1
ST72361xx-Auto
Figure 92
DR0
0
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