ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 162
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
ST72361AR9-Auto
Manufacturer Part Number
ST72361AR9-Auto
Description
8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
Manufacturer
STMicroelectronics
Datasheet
1.ST72361AR9-AUTO.pdf
(279 pages)
Specifications of ST72361AR9-Auto
Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
- Current page: 162 of 279
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LINSCI serial communication interface (LIN master/slave)
162/279
When an overrun error occurs:
●
●
●
●
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.
When noise is detected in a character:
●
●
●
The NF bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Framing error
A framing error is detected when:
●
●
When the framing error is detected:
●
●
●
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Break character
●
Conventional baud rate generation
The baud rates for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
The OR bit is set.
The RDR content will not be lost.
The shift register will be overwritten.
An interrupt is generated if the RIE bit is set and the I[|1:0] bits are cleared in the CCR
register.
The NF bit is set at the rising edge of the RDRF bit.
Data is transferred from the shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The stop bit is not recognized on reception at the expected time, following either a
desynchronization or excessive noise.
A break is received.
the FE bit is set by hardware
Data is transferred from the shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
When a break character is received, the SCI handles it as a framing error. To
differentiate a break character from a framing error, it is necessary to read the SCIDR.
If the received value is 00h, it is a break character. Otherwise it is a framing error.
Tx =
Doc ID 12468 Rev 3
(16
f
CPU
*
PR)
*
TR
Rx =
(16
f
CPU
*
PR)
*
RR
ST72361xx-Auto
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