ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 184

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master/slave)
15.10
15.10.1
Note:
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LIN mode register description
Status register (SCISR)
Read only
Reset value: 1100 0000 (C0h)
Bits 7:4 = same function as in SCI mode, please refer to
description.
Bit 3 = LHE LIN Header Error.
During LIN header this bit signals three error types:
●
●
●
An interrupt is generated if RIE = 1 in the SCICR2 register. If blocked in the LIN synch state,
the LSF bit must first be reset (to exit LIN synch field state and then to be able to clear LHE
flag). Then it is cleared by the following software sequence: An access to the SCISR register
followed by a read to the SCIDR register.
Apart from the LIN header this bit signals an overrun error as in SCI mode, (see description
in
Bit 2 = NF Noise flag
In LIN master mode (LINE bit = 1 and LSLV bit = 0) this bit has the same function as in SCI
mode, please refer to
In LIN slave mode (LINE bit = 1 and LSLV bit = 1) this bit has no meaning.
Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real framing error is detected (if the stop bit is
dominant (0) and at least one of the other bits is recessive (1). It is not set when a break
occurs, the LHDF bit is used instead as a break flag (if the LHDM bit = 0). It is cleared by a
software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error occurs (if the PCE bit is set) in receiver
mode. It is cleared by a software sequence (a read to the status register followed by an
access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1
register.
Section 15.8: SCI mode register
TDRE
The LIN synch field is corrupted and the SCI is blocked in LIN synch state (LSF bit = 1).
A timeout occurred during LIN Header reception
An overrun error was detected on one of the header field (see OR bit description in
Section 15.8: SCI mode register
0: no LIN header error
1: LIN header error detected
0: no Framing error
1: framing error detected
0: no LIN parity error
1: LIN parity error detected
7
TC
Section 15.8: SCI mode register description
RDRF
Doc ID 12468 Rev 3
description)
description).
IDLE
LHE
Section 15.8: SCI mode register
NF
FE
ST72361xx-Auto
PE
0