ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 119

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72361xx-Auto
12.7.4
Note: Reading or writing the ACLR register does not clear TOF.
Bit 6 = OCF1 Output Compare Flag 1.
Bit 5 = TOF Timer Overflow Flag.
Bit 4 = ICF2 Input Capture Flag 2.
Bit 3 = OCF2 Output Compare Flag 2.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it freezes the timer prescaler and counter
and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption.
Access to the timer registers is still available, allowing the timer configuration to be changed,
or the counter reset, while it is disabled.
Bits 1:0 = Reserved, must be kept cleared.
Input capture 1 high register (IC1HR)
Read Only
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
MSB
0: nomatch (reset value).
1: the content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC1R (OC1LR) register.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low byte of the CR (CLR) register.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC2R (OC2LR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
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