TMPM364F10FG Toshiba, TMPM364F10FG Datasheet
TMPM364F10FG
Specifications of TMPM364F10FG
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TMPM364F10FG Summary of contents
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... Bit RISC Microcontroller TX03 Series TMPM364F10FG ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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... ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM364F10FG R ...
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... This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and func- tions. Register name SAMCR TMPM364F10FG Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C ...
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... Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width TDATA Function READ WRITE TMPM364F10FG MODE ...
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... TMPM364F10FG ...
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Date Revision 2011/4/8 Tentative 1 2011/6/20 1 Revision History Comment First Release First Release ...
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...
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... SysTick..............................................................................................................................................................................20 2.3.4 SYSRESETREQ................................................................................................................................................................20 2.3.5 LOCKUP...........................................................................................................................................................................20 2.3.6 Auxiliary Fault Status register..........................................................................................................................................20 2.4 Events......................................................................................................................................21 2.5 Power Management.................................................................................................................21 2.6 Exclusive access......................................................................................................................21 3. Debug Interface 3.1 Specification Overview...........................................................................................................23 3.2 SW-DP.....................................................................................................................................23 3.3 ETM.........................................................................................................................................23 3.4 Pin functions............................................................................................................................24 3.5 Peripheral Functions in Halt Mode.........................................................................................25 3.6 Connection with a Debug Tool...............................................................................................25 4. Memory Map 4.1 Memory Map...........................................................................................................................27 4.1.1 Memory map of the TMPM364F10FG............................................................................................................................28 4.2 SFR area detail........................................................................................................................29 i ...
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Reset 5.1 Cold reset.................................................................................................................................31 5.2 Warm reset...............................................................................................................................33 5.2.1 Reset period.......................................................................................................................................................................33 5.3 After reset................................................................................................................................33 6. Clock / Mode Control 6.1 Features....................................................................................................................................35 6.2 Registers..................................................................................................................................36 6.2.1 Register List.......................................................................................................................................................................36 6.2.2 CGSYSCR (System control register)................................................................................................................................37 6.2.3 CGOSCCR (Oscillation control register).........................................................................................................................39 6.2.4 CGSTBYCR (Standby control ...
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Exception exit 7.2 Reset Exceptions.....................................................................................................................70 7.3 Non-Maskable Interrupts (NMI).............................................................................................70 7.4 SysTick....................................................................................................................................70 7.5 Interrupts..................................................................................................................................71 7.5.1 Interrupt Sources................................................................................................................................................................71 7.5.1.1 Interrupt route 7.5.1.2 Generation 7.5.1.3 Transmission 7.5.1.4 Precautions when using external interrupt pins 7.5.1.5 List of Interrupt Sources 7.5.1.6 Active level 7.5.2 ...
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PACR (Port A output control register) 8.2.1.5 PAFR1 (Port A function register 1) 8.2.1.6 PAOD (Port A open drain control register) 8.2.1.7 PAPUP (Port A pull-up control register) 8.2.1.8 PAIE (Port A input control register) 8.2.2 Port B (PB0 ...
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PHIE (Port H input control register) 8.2.9 Port I (PI0 to PI1)............................................................................................................................................................175 8.2.9.1 Port I Circuit Type 8.2.9.2 Port I register 8.2.9.3 PIDATA (Port I data register) 8.2.9.4 PICR (Port I output control register) 8.2.9.5 PIFR1 (Port I function ...
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PPIE (Port P input control register) 8.3 Block Diagrams of Ports.......................................................................................................219 8.3.1 Port Types........................................................................................................................................................................219 8.3.2 Type T1............................................................................................................................................................................221 8.3.3 Type T2............................................................................................................................................................................222 8.3.4 Type T3............................................................................................................................................................................223 8.3.5 Type T4............................................................................................................................................................................224 8.3.6 Type T5............................................................................................................................................................................225 8.3.7 Type T6............................................................................................................................................................................226 8.3.8 Type T7............................................................................................................................................................................227 8.3.9 Type T8............................................................................................................................................................................228 8.3.10 ...
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Block diagram.......................................................................................................................279 9.4 Description of Registers........................................................................................................280 9.4.1 DMAC register list..........................................................................................................................................................280 9.4.2 DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................281 9.4.3 DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................282 9.4.4 DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................283 9.4.5 DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................284 ...
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Registers..............................................................................................................................334 11.4.1 Register list according to channel.................................................................................................................................334 11.4.2 TBxEN (Enable register)...............................................................................................................................................335 11.4.3 TBxRUN (RUN register)..............................................................................................................................................336 11.4.4 TBxCR (Control register)..............................................................................................................................................337 11.4.5 TBxMOD (Mode register).............................................................................................................................................338 11.4.6 TBxFFCR (Flip-flop control register)...........................................................................................................................340 11.4.7 TBxST (Status register).................................................................................................................................................341 11.4.8 TBxIM (Interrupt mask register)...................................................................................................................................342 11.4.9 TBxUC ...
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Clock Control......................................................................................................................385 12.7.1 Prescaler.........................................................................................................................................................................385 12.7.2 Serial Clock Generation Circuit....................................................................................................................................391 12.7.2.1 Baud Rate Generator 12.7.2.2 Clock Selection Circuit 12.8 Transmit / Receive Buffer and FIFO..................................................................................395 12.8.1 Configuration.................................................................................................................................................................395 12.8.2 Transmit / Receive Buffer.............................................................................................................................................395 12.8.3 FIFO...............................................................................................................................................................................395 12.9 Status Flag...........................................................................................................................396 12.10 Error Flag...........................................................................................................................396 ...
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Register List...................................................................................................................................................................427 13.3.2 SSPCR0(Control register 0)..........................................................................................................................................428 13.3.3 SSPCR1(Control register1)...........................................................................................................................................429 13.3.4 SSPDR(Data register)....................................................................................................................................................430 13.3.5 SSPSR(Status register)..................................................................................................................................................431 13.3.6 SSPCPSR (Clock prescale register)..............................................................................................................................432 13.3.7 SSPIMSC (Interrupt enable/disable register)................................................................................................................433 13.3.8 SSPRIS (Pre-enable interrupt status register)...............................................................................................................434 13.3.9 SSPMIS (Post-enable interrupt status register)............................................................................................................435 13.3.10 SSPICR ...
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Master mode 14.6.2.2 Slave mode 14.6.3 Transferring a Data Word.............................................................................................................................................469 14.6.3.1 Master mode (<MST> = "1") 14.6.3.2 Slave mode (<MST> = "0") 14.6.4 Generating the Stop Condition......................................................................................................................................474 14.6.5 Restart Procedure...........................................................................................................................................................474 14.7 Control register of SIO mode..............................................................................................476 14.7.1 SBIxCR0(control register ...
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CAN Controller 16.1 Overview..............................................................................................................................525 16.2 Block Diagram.....................................................................................................................526 16.3 CAN Interface.....................................................................................................................526 16.4 Register................................................................................................................................527 16.4.1 Register list....................................................................................................................................................................527 16.4.2 CANMBxID (Message ID Field Register)...................................................................................................................529 16.4.3 CANMBxTSVMCF (Time Stamp Values / Message Control Field Register)...........................................................530 16.4.4 CANMBxDH/CANMBxDL (Data fields Register)......................................................................................................531 16.4.5 CANMC (Mailbox ...
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Block Diagram.....................................................................................................................577 17.3 Registers..............................................................................................................................578 17.3.1 Register List...................................................................................................................................................................578 17.3.2 RMCxEN(Enable Register)...........................................................................................................................................579 17.3.3 RMCxREN(Receive Enable Register)..........................................................................................................................580 17.3.4 RMCxRBUF1(Receive Data Buffer Register 1)..........................................................................................................581 17.3.5 RMCxRBUF2(Receive Data Buffer Register 2)..........................................................................................................581 17.3.6 RMCxRBUF3(Receive Data Buffer Register 3)..........................................................................................................582 17.3.7 RMCxRCR1(Receive Control Register 1)....................................................................................................................583 17.3.8 RMCxRCR2(Receive ...
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Setting the USB Clock..................................................................................................................................................635 18.7.2 Oscillator Recommendation..........................................................................................................................................635 18.7.3 Entering SLOW Mode and Low Power Consumption Modes....................................................................................635 18.7.4 When not using USB.....................................................................................................................................................635 18.7.5 Competing access to the RAM0 and the RAM1..........................................................................................................635 18.8 Restrictions on Using the USB Host Controller.................................................................636 18.9 ...
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Backup Transition Flow 21.3.1.3 Transition Flowchart 21.3.1.4 BACKUP Mode Timing Chart 22. Analog / Digital Converter (ADC) 22.1 Outline.................................................................................................................................667 22.2 Configuration.......................................................................................................................668 22.3 Registers..............................................................................................................................669 22.3.1 Register list....................................................................................................................................................................669 22.3.2 ADCBAS (Conversion Accuracy Setting Register).....................................................................................................670 22.3.3 ADCLK (Conversion Clock Setting Register).............................................................................................................671 22.3.4 ...
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RTCRESTR (Reset register (for PAGE0/1)) 23.4 Operational Description.......................................................................................................709 23.4.1 Reading clock data........................................................................................................................................................709 23.4.2 Writing clock data.........................................................................................................................................................709 23.4.3 Entering the Low Power Consumption Mode..............................................................................................................711 23.5 Alarm function.....................................................................................................................712 23.5.1 "Low" pulse (when the alarm register corresponds with the clock)...........................................................................712 23.5.2 1Hz ...
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Writing and erasing.............................................................................................................775 25.4.1 Protection bits................................................................................................................................................................775 25.4.2 Security bit.....................................................................................................................................................................775 26. RAM Interface 26.1 Register List.........................................................................................................................777 26.1.1 RCWAIT(RAM Interface Register) .............................................................................................................................777 27. Electrical Characteristics 27.1 Absolute Maximum Ratings................................................................................................779 27.2 DC Electrical Characteristics (1/3).....................................................................................780 27.3 DC Electrical Characteristics (2/3).....................................................................................781 27.4 DC ...
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MODE, SWCLK.................................................................................................................807 28.7 SWDIO................................................................................................................................807 28.8 X1, X2.................................................................................................................................808 28.9 XT1, XT2............................................................................................................................808 28.10 VREFH, AVSS..................................................................................................................808 29. Package Dimensions xviii ...
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... TMPM364F10FG The TMPM364F10FG is a 32-bit RISC microprocessor series with an ARM Cortex-M3 microprocessor core. Product name TMPM364F10FG Features of the TMPM364F10FG are as follows : 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb-2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ ...
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... Fixed channel / scan mode ・ Single / repeat mode ・ AD monitoring 2 channels ・ Conversion speed 1.15 μsec (@ fsys = 40 MHz) 14. Key-on wake-up (KWUP channels Dynamic pull-up 15. USB host controller : 1 channel ・ Universal serial bus (Rev 2.0 standard) ・ Open HCI for USB Release 1.0a ・ 12Mbps(full speed) Page 2 TMPM364F10FG ...
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... Clock gear function : The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 23. Endian Little endian 24. Maximum operating frequency : 64MHz (48MHz when USB is used.) 25. Operating voltage range 2 3.6 V (with on-chip regulator) 3 3.6 V (when USB is used) 26. Temperature range ・ -40 degrees to 85 degrees (except Flash writing / erasing) Page 3 TMPM364F10FG ...
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... Features ・ 0 degrees to 70 degrees (during Flash writing / erasing) 27. Package LQFP144-P-2020-0.50E ( mm, 0.5 mm pitch) Page 4 TMPM364F10FG ...
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... Block Diagram Cortex-M3 ETM SWD FLASH (1MB) RAM (40KB) Backup RAM (8KB) SMC CAN BOOT ROM Figure 1-1 TMPM364F10FG Block Diagram USB Host DMA Controller Controller NVIC AHB Lite Bus Matrix RAM0 (8KB) RAM1 (8KB) PORT A~K CG PORT WDT RTC 16bit Timer SIO/UART ...
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... Pin layout (Top view) 1.3 Pin layout (Top view) Figure 1-2 shows the pin layout of TMPM364F10FG. PH3/INTC/TBBIN1 PH4/SDA4/SO4/TBDIN0 110 PH5/SCL4/SI4/TBDIN1 PH6/SCK4/TBEIN0 PH7/INTD/TBEIN1 RVDD3 XT1 115 XT2 DVDD3A X1 DVSS X2 120 DVDD3B DVSS D D NMI 125 TEST1 TEST2 PI0/BOOT Pl1/CEC AVDD3 130 PJ0/AIN0 PJ1/AIN1 PJ2/AIN2 ...
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... Pin names and Functions Table 1-1 sort input and output pins of TMPM364F10FG by pin or port. The table includes alternate pin names and function for multi-function pins. 1.4.1 Sorted by pin Table 1-1 Pin Names and Functions Sorted by Pin (1/10) Pin Input / Type PIn Name No. Output PK6 Input ...
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... Serial clock input / output Input Inputting the Timer B capture trigger Input Handshake input pin I/O I/O port Input External interrupt pin Input Inputting the Timer B capture trigger Input Inputting signal to remote controller I/O I/O port Output Sending serial data I/O I/O port Input Receiving serial data Page 8 TMPM364F10FG Function ...
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... Timer B output I/O port Serial clock input / output Timer B output Handshake input pin I/O port External interrupt pin Timer B output I/O port Chip select pin I/O port I/O port Byte lane pin SSP data output pin I/O port Byte lane pin SSP data input pin Page 9 TMPM364F10FG ...
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... Address and data bus I/O I/O port I/O data bus I/O Address and data bus I/O I/O port I/O data bus I/O Address and data bus I/O I/O port I/O data bus I/O Address and data bus I/O I/O port I/O data bus I/O Address and data bus I/O I/O port I/O data bus I/O Address and data bus Page 10 TMPM364F10FG Function ...
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... Receiving serial data I/O port Address bus Serial clock input / output Handshake input pin I/O port Address bus I/O port Address bus Sending serial data I/O port Address bus Receiving serial data I/O port Address bus Serial clock input / output Handshake input pin I/O port Address bus Page 11 TMPM364F10FG ...
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... Input Inputting the Timer B capture trigger I/O I/O port Output Address bus Input Inputting the Timer B capture trigger I/O I/O port Output Address bus Input Inputting the Timer B capture trigger I/O I/O port Output Address bus Output Sending serial data Output CAN sending data Page 12 TMPM364F10FG Function ...
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... I2C mode : data pin - in the SIO mode : receive data pin Inputting the Timer B capture trigger I/O port Inputting and outputting a clock if the serial bus interface operates in the SIO mode. Chip select pin I/O port External interrupt pin Chip select pin Page 13 TMPM364F10FG ...
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... I2C mode : data pin - in the SIO mode : transmit data pin Input Inputting the Timer B capture trigger I/O I/O port I/O If the serial bus interface operates - in the I2C mode : data pin - in the SIO mode : receive data pin Input Inputting the Timer B capture trigger Page 14 TMPM364F10FG Function ...
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... This pin goes into single boot mode by sampling "Low" at the rise of a RESET signal. I/O port CEC pin (note) Nch open drain port Supplying the AD converter with a power supply. (note) AVDD3 must be connected to power supply even if A/D converter is not used. Input port Analog input Input port Analog input Input port Analog input Page 15 TMPM364F10FG ...
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... Key-on wake-up pin Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Page 16 TMPM364F10FG Function ...
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... Pin Numbers and Power Supply Pins Table 1-2 PIn Numbers and Power Supplies Power supply Voltage range DVDD3B 2.7 to 3.6V DVDD3A (When USB is used : 3.0 to 3.6V) AVDD3 RVDD3 Pin No. PIn mane PA,PB,PC,PD,PE,PF,PG,PH,PI,PL,PM 47,89,121 PN,PO,PP,XT1,XT2,RESET,NMI,MODE 117 X1,X2 130 PJ,PK 114 − Page 17 TMPM364F10FG ...
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... Pin Numbers and Power Supply Pins Page 18 TMPM364F10FG ...
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... ARM Limited. This chapter describes the functions unique to the TX03 series that are not explained in that docu- ment. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM364F10FG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M ser- ies processors" in the following URL : http://infocenter.arm.com/help/index.jsp 2 ...
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... SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM364F10FG, the clock that is input from X1 pin dividing used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as " ...
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... The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV in- struction execution event is input, the core returns from low-power consumption mode caused by WFE instruc- tion. TMPM364F10FG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 ...
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... Exclusive access Page 22 TMPM364F10FG ...
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... Debug Interface 3.1 Specification Overview The TMPM364F10FG contains the Serial Wire Debug Port (SW-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell ted pins (TRACEDATA[3:0]) via the on-chip Trace Port Interface Unit (TPIU). For details about SW-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual". ...
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... TRACEDATA1 0 0 TRACEDATA2 0 0 TRACEDATA3 0 0 Page 24 TMPM364F10FG SW debug function Comments Serial Wire Data Input/Output (Always pull-up) Serial Wire Clock (Always pull-down) TRACE Clock Output TRACE DATA Output0 / Serial Wire Viewer Output TRACE DATA Output1 TRACE DATA Output2 TRACE DATA Output3 ...
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... Connection with a Debug Tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connec- ted with external pull-up or pull-down, please pay attention to input level. Page 25 TMPM364F10FG ...
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... Connection with a Debug Tool Page 26 TMPM364F10FG ...
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... Memory Map The memory maps for the TMPM364F10FG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. ...
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... Memory Map 4.1.1 Memory map of the TMPM364F10FG Figure 4-1 shows the memory map of the TMPM364F10FG. Vender-Specific CPU Register Region Fault External Bus Area Fault SFR Fault SFR Fault SFR Fault SFR Fault Backup RAM (8K) Internal RAM (56K) Fault Internal ROM (1024K) Figure 4-1 Memory map ...
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... Reserved Port Timer B (16ch) I2C/SIO(5ch) SIO/UART(12ch) CEC RMC(2ch) 0x400F_001C to 0x400F_001F ADC(16ch) 0x400F_0024 to 0x400F_002F KWUP 0x400F_1010 to 0x400F_107F WDT RTC 0x400F_300D 0x400F_402E to 0x400F_402F CG 0x400F_4036 to 0x4000_4FFF 0x41FF_F000 to 0x41FF_F007 0x41FF_F014 to 0x41FF_F017 FLASH 0x41FF_F018 to 0x41FF_F01B 0x41FF_F024 to 0x41FF_F02C 0x41FF_F033 to 0x41FF_F037 Reserved RAMWAIT Reserved Reserved SMCMOD Page 29 TMPM364F10FG ...
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... SFR area detail Page 30 TMPM364F10FG ...
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... Reset The TMPM364F10FG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual". ...
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... Cold reset Note 1: The power supply must be raised (from 0V to 2.7V speed of 0.1ms/V or slower. Note 2: Turn on the power while the RESET pin is fixed to "Low". When all the power supplies are stabilized within operating volt- age, release the reset. Page 32 TMPM364F10FG ...
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... As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM364F10FG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μ ...
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... After reset Page 34 TMPM364F10FG ...
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... Controls the system clock ・ Controls the prescaler clock ・ Controls the PLL multiplication circuit ・ Controls the warm-up timer In addition to NORMAL mode, the TMPM364F10FG can operate in six types of low power mode to reduce pow- er consumption according to its usage conditions. Page 35 TMPM364F10FG ...
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... The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page 36 TMPM364F10FG Base Address = 0x400F_4000 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 ...
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... Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as "0" FCSTOP - FPSEL1 FPSEL0 - Function Page 37 TMPM364F10FG SCOSEL PRCK GEAR ...
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... Registers Bit Bit Symbol Type 2-0 GEAR[2:0] R/W High-speed clock (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved Page 38 TMPM364F10FG Function ...
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... Starting warm-up Enables to start the warm-up timer WUPT WUPSEL PLLON Function Page 39 TMPM364F10FG XTEN XEN WUEF WUEON ...
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... High-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation Read as "0". Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE2 100: Reserved 101: BACKUP STOP 110: BACKUP SLEEP 111: IDLE1 Page 40 TMPM364F10FG ...
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... Resetting is required when using the PLL Function Page 41 TMPM364F10FG C2S PLLSEL ...
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... Setting CGOSCCR<XEN> and <XTEN> to "1" in advance is required. System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with <SYSCK> generates time lag to complete. If the output of the oscillator specified in <SYSCK> is read out by <SYSCLKFLG>, the switching has been completed. Page 42 TMPM364F10FG ...
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... Reset operation causes all the clock configurations excluding the low-speed clock (fs the same as fosc fosc fsys = fosc φT0 = fosc For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the pin. : fc, fc/2, fc/4, fc/8 : fs, fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 : fsys : fosc/32 : oscillating : oscillating : stop : fc (no frequency dividing) Page 43 TMPM364F10FG ...
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... CGOSCCR<PLLON> Stops after releasing reset fs 1/32 CGSYSCR <FPSEL1> CGSYSCR 1/2 1/4 1/8 1/16 1/32 <PRCK[2:0]> 1/2 Figure 6-1 Clock Block Diagram Page 44 TMPM364F10FG ADC conversion FCSTOP clock <ADCLK> CGSYSCR<FPSEL0> fperiph ( I/O ) fgear fsys 1/8 CGSYSCR CGCKSEL <GEAR[2:0]> <SYSCK> fs Systick Timer input CPU(STCLK) φT0 ...
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... CGOSCCR <PLLON> = “0” (PLL stop) must be retained 100μs or more for stablization. By setting CGOSCCR<PLLON>=” 1”→“0” (PLL stop), multiplier factor will be initialized to “4” . Starting PLL operation needs to approximately 200μs or more stablization time by retaining CGOSCCR<PLLON>= “1” (PLL on). Page 45 TMPM364F10FG ...
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... It takes 100μs or more for the PLL to be stabilized when changed PLL setting to hole the CGOSCCR<PLLON>= “0” (PLL stop) It takes approx 200μs for the PLL to be stabilized. To hold the CGOSCCR<PLLON>=” 1” (PLL active). Figure 6-3 Changing the PLL setting Page 46 TMPM364F10FG Note ...
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... Check warm-up counter setting : Enable high-speed oscillation (fosc) : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to high-speed (fgear) : Wait for "0" (the current clock is fgear) : Disable the low-speed oscillation (fs) (In dual clock mode, it’s not required.) Page 47 TMPM364F10FG ...
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... Enable low-speed oscillation (fs) : Select XT1 for warm-up clock : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to low-speed (fs) : Wait for "1" (the current clock is fs) : Disable the high-speed oscillation (fc) (In dual clock mode, it’s not required.) Page 48 TMPM364F10FG ...
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... System Clock The TMPM364F10FG offers two selectable system clocks: low-speed or high-speed. The high-speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The ac- tual switching takes place after a slight delay. Note 2: When PLL is used as octuple, do not use the oscillator which is upper than 8MHz. ...
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... System Clock Pin Output Function TMPM364F10FG enables to output the system clock from a pin. The SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. The out- put clock is selected by setting the CGSYSCR<SCOSEL[1:0]>. ...
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... When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Also, TMPM364F10FG has a BACKUP mode. This mode can reduce power consumption of full width by shutdown main power supply of almost function except particular one. ...
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... Note 1: Be sure to stop peripheral functions except for the CPU, TMRB, RTC, I/O ports, CEC, RMC and KWUP be- fore switching to the SLOW mode. Note 2: In the SLOW mode, be sure not to perform reset using the Application Interrupt and Reset Control Regis- ter <SYSRESETREQ> of the Cortex-M3 NVIC register. Page 52 TMPM364F10FG ...
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... Releasing by the interrupt requires settings in advance. See the chapter "Exceptions" for details. Note 1: The TMPM364F10FG does not offer any event for releasing the low power consumption mode. Transition to the low power consumption mode by executing the WFE (Wait For Event) instruction is prohibited. ...
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... Pin name I/O Input only Output only Input only Input Output Input Output Input Output Input Output Input Output Page 54 TMPM364F10FG <DRVE> <DRVE> × × "High" level output "High" level output ο ο ο ο × Depends on (PxCR[m]) ο ο × Depends on (PxCR[m]) × ...
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... Table 6-6 shows the mode setting in the <STBY[2:0]>. Table 6-6 Low power consumption mode setting BACKUP SLEEP Note:Do not use reserved mode setting. CGSTBYCR Mode <STBY[2:0]> Reserved 000 STOP 001 SLEEP 010 IDLE2 011 Reserved 100 BACKUP STOP 101 110 IDLE1 111 Page 55 TMPM364F10FG ...
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... Page 56 TMPM364F10FG BACKUP SLEEP STOP SLEEP − − × − − × ο ο × − − × ο (note 6) ο (note 2) Δ (note 3) Δ ...
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... Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-8. Page 57 TMPM364F10FG ...
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... Page 58 TMPM364F10FG BACKUP BACKUP SLEEP STOP (note 2) (note 2) ο ο × × ο × × × × × × × × × ...
Page 85
... Auto-warm-up (note 3) High-speed oscillator : more than 100μs Auto-warm-up High-speed oscillator : Setting value of warm-up time Not required Auto-warm-up High-speed oscillator : Setting value of warm-up time Auto-warm-up Low-speed oscillator :Setting value of warm-up time Auto-warm-up (note 3) High-speed oscillator : more than 500μs Page 59 TMPM364F10FG ...
Page 86
... Table 6-9 Warm-up setting in mode transition Mode transition Warm-up setting Auto-warm-up (note 3) BACKUP STOP → NORMAL High-speed oscillator : more than Auto-warm-up (note 3) BACKUP SLEEP → SLOW Low-speed oscillator : more than Auto-warm-up (note 3) BACKUP STOP → SLOW Low-speed oscillator : more than Page 60 TMPM364F10FG 500μs 2.5ms 2.5ms ...
Page 87
... System clock stops Release event occurs STOP High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Release event occurs SLEEP Oscillation continues High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Page 61 TMPM364F10FG NORMAL NORMAL ...
Page 88
... WFI excute/ sleep on exit Release event occurs STOP System clock stops Low-speed clock starts oscillating Warm-up starts WFI excute/ sleep on exit SLEEP System clock stops Page 62 TMPM364F10FG SLOW Warm-up completes System clock starts Release event occurs SLOW System clock starts ...
Page 89
... For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ Reset ・ Non-Maskable Interrupt (NMI) ・ Hard Fault ・ Memory Management ・ Bus Fault ・ Usage Fault ・ SVCall (Supervisor Call) ・ Debug Monitor ・ PendSV ・ SysTick ・ External Interrupt Page 63 TMPM364F10FG ...
Page 90
... Description The CG/CPU detects the exception request. The CPU handles the exception request. The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. The CPU branches to another ISR or returns to the previous program. Page 64 TMPM364F10FG See Section 7.1.2.1 Section 7.1.2.2 Section 7.1.2.4 Section 7.1.2.4 ...
Page 91
... Access violation to the Hard Fault region of the memory map Undefined instruction execution or other faults related to instruction ex- ecution System service call with SVC instruction Debug monitor when the CPU is not faulting Pendable system service request Notification from system timer External interrupt pin or peripheral function (Note2) Page 65 TMPM364F10FG ...
Page 92
... Pre-emption Subpriority field field [7:1] [0] [7:2] [1:0] [7:3] [2:0] [7:4] [3:0] [7:5] [4:0] [7:6] [5:0] [7] [6:0] None [7:0] ple, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0] > is "00000". Page 66 TMPM364F10FG Number of Number of pre-emption subpriorities priorities 128 128 1 256 ...
Page 93
... A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre- sponding ISR, but the CPU does not newly push the register contents to the stack. (4) Vector table The vector table is configured as shown below. Old SP → <previous> xPSR PC LR r12 → r0 Page 67 TMPM364F10FG ...
Page 94
... Bus Fault ISR address Usage Fault ISR address Reserved SVCall ISR address Debug Monitor ISR address Reserved PendSV ISR address SysTick ISR address External Interrupt ISR address Page 68 TMPM364F10FG Setting Required Required Required Required Optional Optional Optional Optional Optional Optional Optional Optional ...
Page 95
... Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. ・ Select SP If returning to an exception (Handler Mode SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 69 TMPM364F10FG ...
Page 96
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms tim- ing when the clock input from MHz. Page 70 TMPM364F10FG ...
Page 97
... External Port interrupt pin Peripheral function 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. Interrupt request <INTxEN> Exiting standby mode Clock generator Figure 7-1 Interrupt Route Page 71 TMPM364F10FG CPU ...
Page 98
... Set the port control register so that the external pin can perform as an interrupt function pin. Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pend- Page 72 TMPM364F10FG ...
Page 99
... AD conversion monitoring function interrupt 1 40 INTTB0 16-bit TMRB match detection 0 41 INTTB1 16-bit TMRB match detection 1 42 INTTB2 16-bit TMRB match detection 2 active level (Clearing standby) Selectable - Rising edge Falling edge High level Page 73 TMPM364F10FG CG interrupt mode control register CGIMCGA CGIMCGB CGIMCGC CGIMCGD - CGIMCGE CGIMCGF ...
Page 100
... TMRB input capture 50 16-bit TMRB input capture 51 16-bit TMRB input capture 60 16-bit TMRB input capture 61 16-bit TMRB input capture 70 16-bit TMRB input capture 71 16-bit TMRB input capture 90 16-bit TMRB input capture 91 Page 74 TMPM364F10FG active level CG interrupt mode (Clearing standby) control register ...
Page 101
... Note:For the CEC reception / transmission, remote control signal reception and real time clock in- terrupts, set the <INTxEN> bit to "1" and specify the active level, even when they are not used for clearing a standby mode. active level (Clearing standby) Page 75 TMPM364F10FG CG interrupt mode control register ...
Page 102
... If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. The CPU handles the interrupt. The CPU pushes register contents to the stack before entering the ISR. Page 76 TMPM364F10FG See "7.5.2.2 Preparation" "7.5.2.3 Detection by Clock Generator" ...
Page 103
... Processing Program for the ISR. ISR execution Clear the interrupt source if needed. Return to preceding Configure to return to the preceding program of the ISR. program Details Page 77 TMPM364F10FG See "7.5.2.6 Interrupt Serv- ice Routine (ISR)" ...
Page 104
... Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority lev- el.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. ← "1"(Interrupt disabled) Page 78 TMPM364F10FG ...
Page 105
... Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the interrupt to be used to the CGICRCG register.See "7.6.3.7 CGICRCG (CG Interrupt Request Clear Register)" for each value. Page 79 TMPM364F10FG ...
Page 106
... If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt request in the ISR. ← active level ← Value corresponding to the interrupt to be used ← "1" (interrupt enabled) ← "1" ← "1" ← "0" Page 80 TMPM364F10FG ...
Page 107
... Therefore, the interrupt source must be cleared. Clearing the interrupt source au- tomatically clears the interrupt request signal from the clock generator interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding val the CGICRCG register. When an active edge occurs again, a new interrupt request will be detec- ted. Page 81 TMPM364F10FG ...
Page 108
... Reserved Reserved Note:Access to the "Reserved" areas is prohibited. Register name Register name CGICRCG CGNMIFLG CGRSTFLG CGIMCGA CGIMCGB CGIMCGC CGIMCGD CGIMCGE CGIMCGF - - Page 82 TMPM364F10FG Base Address = 0xE000_E000 Address 0x0010 0x0014 0x0018 0x001C 0x0100 0x0104 0x0108 0x010C 0x0180 0x0184 0x0188 0x018C 0x0200 0x0204 0x0208 ...
Page 109
... If "1" is set, it reloads with the value of the Reload Value Register and starts operation CLKSOURCE Function Page 83 TMPM364F10FG COUNTFLAG TICKINT ENABLE ...
Page 110
... Undefined CURRENT Undefined Read as 0. [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears Clearing this register also clears the <COUNTFLAG> bit of the SysTick Control and Status Register. Page 84 TMPM364F10FG ...
Page 111
... SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from MHz TENMS TENMS TENMS Function Page 85 TMPM364F10FG ...
Page 112
... Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 86 TMPM364F10FG SETENA SETENA ...
Page 113
... SETENA SETENA SETENA (Interrupt 44) (Interrupt 43) (Interrupt 42 SETENA SETENA SETENA (Interrupt 36) (Interrupt 35) (Interrupt 34 Function Page 87 TMPM364F10FG SETENA SETENA SETENA (Interrupt 57) (Interrupt 56 SETENA SETENA SETENA (Interrupt 49) (Interrupt 48 SETENA SETENA ...
Page 114
... Page 88 TMPM364F10FG SETENA SETENA SETENA (Interrupt 91) (Interrupt 90) (Interrupt 89 SETENA SETENA SETENA (Interrupt 83) (Interrupt 82) (Interrupt 81 SETENA SETENA SETENA (Interrupt 75) (Interrupt 74) (Interrupt 73 ...
Page 115
... Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Function Page 89 TMPM364F10FG ...
Page 116
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 90 TMPM364F10FG CLRENA ...
Page 117
... CLRENA CLRENA CLRENA (Interrupt 44) (Interrupt 43) (Interrupt 42 CLRENA CLRENA CLRENA (Interrupt 36) (Interrupt 35) (Interrupt 34 Function Page 91 TMPM364F10FG CLRENA CLRENA CLRENA (Interrupt 57) (Interrupt 56 CLRENA CLRENA CLRENA (Interrupt 49) (Interrupt 48 CLRENA CLRENA ...
Page 118
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 92 TMPM364F10FG CLRENA ...
Page 119
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRENA CLRENA - - (Interrupt 99) (Interrupt 98 Function Page 93 TMPM364F10FG CLRENA CLRENA (Interrupt 97) (Interrupt 96 ...
Page 120
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Page 94 TMPM364F10FG SETPEND ...
Page 121
... Undefined SETPEND SETPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined SETPEND SETPEND (Interrupt 36) (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 95 TMPM364F10FG SETPEND SETPEND SETPEND (Interrupt 57) (Interrupt 56) Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined ...
Page 122
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Page 96 TMPM364F10FG SETPEND ...
Page 123
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" SETPEND SETPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 97 TMPM364F10FG SETPEND SETPEND (Interrupt 97) (Interrupt 96) Undefined Undefined ...
Page 124
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 98 TMPM364F10FG ...
Page 125
... CLRPEND CLRPEND CLRPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND (Interrupt 36) (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 99 TMPM364F10FG CLRPEND CLRPEND (Interrupt 57) (Interrupt 56) Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined CLRPEND ...
Page 126
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 100 TMPM364F10FG ...
Page 127
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRPEND CLRPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 101 TMPM364F10FG CLRPEND CLRPEND (Interrupt 97) (Interrupt 96) Undefined Undefined ...
Page 128
... PRI_62 PRI_67 PRI_66 PRI_71 PRI_70 PRI_75 PRI_74 PRI_79 PRI_78 PRI_83 PRI_82 PRI_87 PRI_86 PRI_91 PRI_90 PRI_95 PRI_94 PRI_99 PRI_98 Page 102 TMPM364F10FG PRI_1 PRI_0 PRI_5 PRI_4 PRI_9 PRI_8 PRI_13 PRI_12 PRI_17 PRI_16 PRI_21 PRI_20 PRI_25 PRI_24 PRI_29 PRI_28 PRI_33 ...
Page 129
... Function Page 103 TMPM364F10FG − − − − − − − − − − ...
Page 130
... The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for interrupts.For more interrupts, you must adjust the align- ment by rounding up to the next power of two. Read as 0, Page 104 TMPM364F10FG TBLOFF ...
Page 131
... Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is cleared by warm reset VECTKEY/VECTKEYSTAT VECTKEY/VECTKEYSTAT SYSRESET - - - REQ Function Page 105 TMPM364F10FG PRIGROUP VECTCLR VECTRESET ACTIVE ...
Page 132
... PRI_4 - Reserved Read as 0, Priority of Usage Fault Read as 0, Priority of Bus Fault Read as 0, Priority of Memory Management Read as 0, Page 106 TMPM364F10FG PRI_5 PRI_4 (Bus Fault) (Memory Management) PRI_9 PRI_8 PRI_13 PRI_12 (Debug Monitor ...
Page 133
... USGFAULT - - - USGFAULT SYSTICKACT PENDSVACT PENDED PENDED USGFAULT - - ACT Function Page 107 TMPM364F10FG BUSFAULT MEMFAULT ENA ENA ENA MONITOR - ACT BUSFAULT MEMFAULT - ...
Page 134
... MEMFAULT R/W ACT Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not re- pair stack contents. Usage Fault 0: Inactive 1: Active Read as 0, Bus Fault 0: Inactive 1: Active Memory management 0: Inactive 1: Active Page 108 TMPM364F10FG Function ...
Page 135
... R Read EMCG3 EMST3 EMCG2 EMST2 EMCG1 EMST1 EMCG0 EMST0 Function Page 109 TMPM364F10FG INT3EN 0 Undefined INT2EN 0 Undefined INT1EN 0 Undefined INT0EN 0 Undefined 0 ...
Page 136
... INT0 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT0 clear input 0: Disable 1: Enable Page 110 TMPM364F10FG Function ...
Page 137
... Both edge EMCG7 EMST7 EMCG6 EMST6 EMCG5 EMST5 EMCG4 EMST4 Function Page 111 TMPM364F10FG INT7EN 0 Undefined INT6EN 0 Undefined INT5EN 0 Undefined INT4EN 0 Undefined 0 ...
Page 138
... INT4 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT4 clear input 0: Disable 1: Enable Page 112 TMPM364F10FG Function ...
Page 139
... Both edge EMCGB EMSTB EMCGA EMSTA EMCG9 EMST9 EMCG8 EMST8 Function Page 113 TMPM364F10FG INTBEN 0 Undefined INTAEN 0 Undefined INT9EN 0 Undefined INT8EN 0 Undefined 0 ...
Page 140
... INT8 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT8 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT8 clear input 0: Disable 1: Enable Page 114 TMPM364F10FG Function ...
Page 141
... Rising edge 10: Falling edge 11: Both edge 1 − R Reads as undefined EMCGD EMSTD EMCGC EMSTC Function Page 115 TMPM364F10FG Undefined Undefined INTDEN 0 Undefined INTCEN 0 Undefined 0 ...
Page 142
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro- hibited. INTC clear input 0: Disable 1: Enable Page 116 TMPM364F10FG Function ...
Page 143
... INTCECTX Clear input 0:Disable 1: Enable EMCGJ EMSTJ EMCGI EMSTI EMCGH EMSTH EMCGG EMSTG Function Page 117 TMPM364F10FG INTJEN 0 Undefined INTIEN 0 Undefined INTHEN 0 Undefined INTGEN 0 Undefined 0 ...
Page 144
... Read as 0, active level setting of INTCECRX standby clear request. Set it as shown below. 011: Rising edge active level of INTCECRX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge Read as undefined. INTCECRX Clear input 0:Disable 1: Enable Page 118 TMPM364F10FG Function ...
Page 145
... Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro- hibited EMCGL EMSTL EMCGK EMSTK Function Page 119 TMPM364F10FG INTLEN 0 Undefined INTKEN 0 Undefined 0 ...
Page 146
... INT8 0_0001: INT1 0_1001: INT9 0_0010: INT2 0_1010: INTA 0_0011: INT3 0_1011: INTB 0_0100: INT4 0_1100: INTC 0_0101: INT5 0_1101: INTD 0_0110: INT6 0_1110: Reserved 0_ 0111: INT7 0_1111: Reserved Read as 0. Page 120 TMPM364F10FG ...
Page 147
... WDT Note:<NMIFLG> are cleared to "0" when they are read Function Page 121 TMPM364F10FG NMIFLG1 NMIFLG0 ...
Page 148
... Reset from BACKUP mode release WDT reset flag 0: "0" is written 1: Reset from WDT RESET pin flag 0: "0" is written 1: Reset from RESET pin Power-on flag 0: "0" is written 1: Reset from power-on reset Page 122 TMPM364F10FG ...
Page 149
... Input / Output Ports 8.1 Port Functions 8.1.1 Function list TMPM364F10FG has 118 ports. Besides the ports function, these ports can be used as I/O pins for peripher- al functions. Table 8-1 shows the port function table. Table 8-1 Port Function List Input / Port PIn Output Port A PA0 I/O PA1 I/O PA2 ...
Page 150
... Pull-up ο − Input Pull-up ο − Input Pull-up ο − Input Pull-up ο ο Page 124 TMPM364F10FG Program- mable Function pin Open-drain ο A14 , RXD11 ο A15 , SCLK11 , CTS11 ο A16 , INTB ο A17 , TB5IN0 ο A18 , TB5IN1 ο A19 , TB6IN0 ο ...
Page 151
... SCLK5 , TBFIN0 , CTS5 ο ο ο INT8 , TBFIN1 , RMC1 ο − ο TXD6 , TB8OUT ο − ο RXD6 , TB9OUT ο − ο SCLK6 , TBAOUT , CTS6 ο ο ο INT9 , TBBOUT ο − ο TXD7 , TBCOUT Page 125 TMPM364F10FG ...
Page 152
... I/O Pull-up − − I/O Pull-up − − I/O Pull-up − − I/O Pull-up ο − Page 126 TMPM364F10FG Program- mable Function pin Open-drain ο RXD7 , TBDOUT ο SCLK7 , TBEOUT , CTS7 ο INTA , TBFOUT ο CS2 ο − ο BLS0 , SPDO ο BLS1 , SPDI ο ...
Page 153
... When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control programmable pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE : Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. Page 127 TMPM364F10FG ...
Page 154
... Pin name I/O Input only Output only Input only Input Output Input Output Input Output Input Output Input Output Page 128 TMPM364F10FG <DRVE> <DRVE> × × "High" Level Output "High"Level Output ο ο ο ο × Depend on PxCR[m] ο ο × Depend on PxCR[m] × ...
Page 155
... Port A open drain control register Port A pull-up control register Port A input control register Register name PADATA PACR PAFR1 PAOD PAPUP PAIE Page 129 TMPM364F10FG Base Address = 0x400C_0000 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 156
... Port A data register PA6C PA5C PA4C Read as 0. Output 0: Disable 1: Enable Page 130 TMPM364F10FG PA3 PA2 PA1 Function ...
Page 157
... D2, AD2 1 PA1F1 R/W 0: PORT 1: D1, AD1 0 PA0F1 R/W 0: PORT 1: D0, AD0 PA5F1 PA4F1 PA3F1 Function Page 131 TMPM364F10FG PA2F1 PA1F1 PA0F1 ...
Page 158
... CMOS 1 : Open-drain PA6UP PA5UP PA4UP Read as 0. Pull-Up 0: Disable 1: Enable Page 132 TMPM364F10FG PA3OD PA2OD PA1OD Function ...
Page 159
... Type 31-8 − R Read as 0. 7-0 PA7IE to PA0IE R/W Input 0: Disable 1: Enable PA5IE PA4IE PA3IE Function Page 133 TMPM364F10FG PA2IE PA1IE PA0IE ...
Page 160
... Port B open drain control register Port B pull-up control register Port B input control register Register name PBDATA PBCR PBFR1 PBOD PBPUP PBIE Page 134 TMPM364F10FG Base Address = 0x400C_0100 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 0 T1 ...
Page 161
... PB5 PB4 PB3 Function PB5C PB4C PB3C Function Page 135 TMPM364F10FG PB2 PB1 PB0 ...
Page 162
... PB6F1 PB5F1 PB4F1 Read PORT 1 : D15, AD15 0: PORT 1: D14, AD14 0: PORT 1: D13, AD13 0: PORT 1: D12, AD12 0: PORT 1: D11, AD11 0: PORT 1: D10, AD10 0: PORT 1: D9, AD9 0: PORT 1: D8, AD8 Page 136 TMPM364F10FG ...
Page 163
... PB5OD PB4OD PB3OD Function PB5UP PB4UP PB3UP Function Page 137 TMPM364F10FG PB2OD PB1OD PB0OD ...
Page 164
... PB7IE to PB0IE R PB6IE PB5IE PB4IE Read as 0. Input 0: Disable 1: Enable Page 138 TMPM364F10FG PB3IE PB2IE PB1IE Function ...
Page 165
... Port C open drain control register Port C pull-up control register Port C input control register Base Address = 0x400C_0200 PCDATA PCCR PCFR1 PCFR2 PCFR3 PCOD PCPUP PCIE Page 139 TMPM364F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 166
... Port C data register PC6C PC5C PC4C Read as 0. Output 0: Disable 1: Enable Page 140 TMPM364F10FG PC3 PC2 PC1 Function ...
Page 167
... PC2F1 R/W 0: PORT PC1F1 R/W 0: PORT PC0F1 R/W 0: PORT PC5F1 PC4F1 PC3F1 Function Page 141 TMPM364F10FG PC2F1 PC1F1 PC0F1 ...
Page 168
... PC6F2 PC5F2 PC4F2 Read PORT 1:SCLK9 0: PORT 1: RXD9 0: PORT 1: TXD9 Read PORT 1: SCLK8 0: PORT 1: RXD8 0: PORT 1: TXD8 Page 142 TMPM364F10FG PC2F2 PC1F2 0 0 ...
Page 169
... Function PC5OD PC4OD PC3OD Function Page 143 TMPM364F10FG PC2F3 - - ...
Page 170
... Disable 1: Enable PC6IE PC5IE PC4IE Read as 0. Input 0: Disable 1: Enable Page 144 TMPM364F10FG PC3UP PC2UP PC1UP Function ...
Page 171
... Port D open drain control register Port D pull-up control register Port D input control register Base Address = 0x400C_0300 PDDATA PDCR PDFR1 PDFR2 PDFR3 PDOD PDPUP PDIE Page 145 TMPM364F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 172
... Port D data register PD6C PD5C PD4C Read as 0. Output 0: Disable 1: Enable Page 146 TMPM364F10FG PD3 PD2 PD1 Function ...
Page 173
... PD2F1 R/W 0: PORT 1: A11 1 PD1F1 R/W 0: PORT 1: A10 0 PD0F1 R/W 0: PORT PD5F1 PD4F1 PD3F1 Function Page 147 TMPM364F10FG PD2F1 PD1F1 PD0F1 ...
Page 174
... PD6F2 PD5F2 PD4F2 Read PORT 1 : INTB 0: PORT 1:SCLK11 0: PORT 1: RXD11 0: PORT 1: TXD11 Read PORT 1: SCLK10 0: PORT 1: RXD10 0: PORT 1: TXD10 Page 148 TMPM364F10FG PD2F2 PD1F2 ...
Page 175
... Function PD5OD PD4OD PD3OD Function Page 149 TMPM364F10FG PD2F3 - - ...
Page 176
... Disable 1: Enable PD6IE PD5IE PD4IE Read as 0. Input 0: Disable 1: Enable Page 150 TMPM364F10FG PD3UP PD2UP PD1UP Function ...
Page 177
... Port E open drain control register Port E pull-up control register Port E input control register T37 T36 T3 T3 Base Address = 0x400C_0400 PEDATA PECR PEFR1 PEFR2 PEFR3 PEOD PEPUP PEIE Page 151 TMPM364F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 178
... Port E data register PE6C PE5C PE4C Read as 0. Output 0: Disable 1: Enable Page 152 TMPM364F10FG PE3 PE2 PE1 Function ...
Page 179
... PE2F1 R/W 0: PORT 1: A19 1 PE1F1 R/W 0: PORT 1: A18 0 PE0F1 R/W 0: PORT 1: A17 PE5F1 PE4F1 PE3F1 Function Page 153 TMPM364F10FG PE2F1 PE1F1 PE0F1 ...
Page 180
... PE6F2 PE5F2 PE4F2 Read PORT 1 : INT5 0: PORT 1:SCLK0 0: PORT 1: RXD0 0: PORT 1: TXD0 0 : PORT 1 : TB6IN1 0: PORT 1: TB6IN0 0: PORT 1: TB5IN1 0: PORT 1: TB5IN0 Page 154 TMPM364F10FG PE3F2 PE2F2 ...
Page 181
... PE5F3 PE4F3 - Function PE5OD PE4OD PE3OD Function Page 155 TMPM364F10FG ...
Page 182
... Disable 1: Enable PE6IE PE5IE PE4IE Read as 0. Intput 0: Disable 1: Enable Page 156 TMPM364F10FG PE3UP PE2UP PE1UP Function ...
Page 183
... Port F function register 1 Port F open drain control register Port F pull-up control register Port F input control register − Base Address = 0x400C_0500 PFDATA PFCR PFFR1 PFOD PFPUP PFIE Page 157 TMPM364F10FG Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 184
... Read as 0. Port F data register PF4C Read as 0. Output 0: Disable 1: Enable Page 158 TMPM364F10FG PF3 PF2 PF1 Function ...
Page 185
... PF2F1 R/W 0: PORT 1: TRACEDATA1 1 PF1F1 R/W 0: PORT 1: TRACEDATA0 / SWV 0 PF0F1 R/W 0: PORT 1: TRACECLK PF4F1 PF3F1 PF2F1 Function Page 159 TMPM364F10FG PF1F1 PF0F1 ...
Page 186
... Read CMOS 1 : Open-drain PF4UP PF3UP Read as 0. Pull-up 0: Disable 1: Enable Page 160 TMPM364F10FG PF2OD PF1OD PF0OD Function ...
Page 187
... Bit Symbol Type 31-5 − R Read as 0. 4-0 PF4IE to PF0IE R/W Input 0: Disable 1: Enable PF4IE PF3IE PF2IE Function Page 161 TMPM364F10FG PF1IE PF0IE ...
Page 188
... Port G pull-up control register Port G input control register T38 T8 T8 Register name PGDATA PGCR PGFR1 PGFR2 PGFR3 PGOD PGPUP PGIE Page 162 TMPM364F10FG T10 T9 T8 Base Address = 0x400C_0600 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 T8 ...
Page 189
... PG5 PG4 PG3 Function PG5C PG4C PG3C Function Page 163 TMPM364F10FG PG2 PG1 PG0 ...
Page 190
... PG6F1 PG5F1 PG4F1 Read PORT 1:INT7 0: PORT 1: SCK2 0: PORT 1: SCL2 / SI2 0: PORT 1: SDA2 / SO2 0: PORT 1: INT6 0: PORT 1: SCK1 0: PORT 1: SCL1 / SI1 0: PORT 1: SDA1 / SO1 Page 164 TMPM364F10FG ...
Page 191
... PORT 1: TB9IN0 3-2 − R Read PG1F2 R/W 0: PORT 1: TB7IN1 0 PG0F2 R/W 0: PORT 1: TB7IN0 PG5F2 PG4F2 - Function Page 165 TMPM364F10FG PG1F2 PG0F2 ...
Page 192
... PG6F3 - - Read PORT 1 : WDTOUT 0 : PORT 1 : CS3 Read PORT 1 : CS1 0 : PORT 1 : CS0 Read as 0. Page 166 TMPM364F10FG PG3F3 PG2F3 - Function 24 - ...
Page 193
... PG5OD PG4OD PG3OD Function PG5UP PG4UP PG3UP Function Page 167 TMPM364F10FG PG2OD PG1OD PG0OD ...
Page 194
... PG7IE to R/W PG0IE PG6IE PG5IE PG4IE Read as 0. Input 0: Disable 1: Enable Page 168 TMPM364F10FG PG3IE PG2IE PG1IE Function ...
Page 195
... Port H open drain control register Port H pull-upcontrol register Port H input control register T12 T12 T13 T12 Base Address = 0x400C_0700 PHDATA PHCR PHFR1 PHFR2 PHOD PHPUP PHIE Page 169 TMPM364F10FG T12 T12 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 ...
Page 196
... Port H data register PH6C PH5C PH4C Read as 0. Output 0: Disable 1: Enable Page 170 TMPM364F10FG PH3 PH2 PH1 Function ...
Page 197
... SCK3 1 PH1F1 R/W 0: PORT 1: SCL3 / SI3 0 PH0F1 R/W 0: PORT 1: SDA3 / SO3 PH5F1 PH4F1 PH3F1 Function Page 171 TMPM364F10FG PH2F1 PH1F1 PH0F1 ...
Page 198
... PH6F2 PH5F2 PH4F2 Read PORT 1: TBEIN1 0: PORT 1: TBEIN0 0: PORT 1: TBDIN1 0: PORT 1: TBDIN0 0: PORT 1: TBBIN1 0: PORT 1: TBBIN0 0: PORT 1: TBAIN1 0: PORT 1: TBAIN0 Page 172 TMPM364F10FG PH3F2 PH2F2 ...
Page 199
... PH5OD PH4OD PH3OD Function PH5UP PH4UP PH3UP Function Page 173 TMPM364F10FG PH2OD PH1OD PH0OD ...
Page 200
... PH7IE to R/W PH0IE PH6IE PH5IE PH4IE Read as 0. Input 0: Disable 1: Enable Page 174 TMPM364F10FG PH3IE PH2IE PH1IE Function ...