TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 145

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TMPM364F10FG

Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM364F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM364F10FG
Manufacturer:
Toshiba
Quantity:
10 000
Company:
Part Number:
TMPM364F10FG
Quantity:
6 000
31-15
14-12
11-10
9
8
7
6-4
3-2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
7.6.3.6
Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising and falling edge. The active level used
Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro-
EMCGL[2:0]
EMSTL[1:0]
INTLEN
EMCGK[2:0]
EMSTK[1:0]
INTKEN
Bit Symbol
for the reset of standby can be checked by referring <EMSTx>. If interrupts are cleared with the CGICRCG register,
<EMSTx> is also cleared.
hibited.
CGIMCGF (CG Interrupt Mode Control Register F)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R
R/W
R
R/W
R
R
R/W
Type
30
22
14
0
0
0
6
0
Read as 0,
active level setting of INTKWUP standby clear request
Set it as shown below.
001: "H" level
active level of INTKWUP standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Read as undefined.
INTKWUP clear input
0: Disable
1: Enable
Read as 0,
active level setting of INTRTC standby clear request
Set it as shown below.
010: Falling edge
active level of INTRTC standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Read as undefined.
INTRTC clear input
0: Disable
1: Enable
-
-
EMCGL
EMCGK
29
21
13
0
0
1
5
1
-
-
Page 119
28
20
12
0
0
0
4
0
-
-
27
19
11
Function
0
0
0
3
0
-
-
EMSTK
EMSTL
26
18
10
0
0
0
2
0
-
-
Undefined
Undefined
25
17
0
0
9
1
-
-
-
-
TMPM364F10FG
INTLEN
INTKEN
24
16
0
0
8
0
0
0
-
-

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