TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 24

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

24. Flash
25. ROM protection
xvi
23.4 Operational Description.......................................................................................................709
23.5 Alarm function.....................................................................................................................712
24.1 Flash Memory......................................................................................................................715
24.2 Operation Mode...................................................................................................................718
24.3 On-board Programming of Flash Memory (Rewrite/Erase)...............................................756
25.1 Outline.................................................................................................................................771
25.2 Future...................................................................................................................................771
25.3 Register................................................................................................................................772
23.4.1
23.4.2
23.4.3
23.5.1
23.5.2
23.5.3
24.1.1
24.1.2
24.2.1
24.2.2
24.2.3
24.2.4
24.2.5
24.2.6
24.2.7
24.2.8
24.2.9
24.2.10
24.2.11
24.3.1
24.3.2
25.2.1
25.2.2
25.3.1
25.3.2
23.3.3.11
24.2.2.1
24.2.2.2
24.2.3.1
24.2.9.1
24.2.9.2
24.2.9.3
24.2.9.4
24.2.10.1
24.2.10.2
24.2.10.3
24.2.10.4
24.2.10.5
24.2.10.6
24.2.10.7
24.2.10.8
24.2.10.9
24.3.1.1
24.3.1.2
24.3.1.3
24.3.1.4
24.3.1.5
24.3.1.6
24.3.2.1
Reading clock data........................................................................................................................................................709
Writing clock data.........................................................................................................................................................709
Entering the Low Power Consumption Mode..............................................................................................................711
1Hz cycle "Low" pulse..................................................................................................................................................713
16Hz cycle "Low" pulse................................................................................................................................................713
Features..........................................................................................................................................................................715
Block Diagram of the Flash Memory Section..............................................................................................................717
Reset Operation.............................................................................................................................................................719
User Boot Mode (Single chip mode)............................................................................................................................719
Single Boot Mode..........................................................................................................................................................728
Configuration for Single Boot Mode............................................................................................................................731
Memory Map.................................................................................................................................................................731
Interface specification....................................................................................................................................................733
Data Transfer Format....................................................................................................................................................734
Restrictions on internal memories.................................................................................................................................734
Transfer Format for Boot Program...............................................................................................................................734
Flash Memory................................................................................................................................................................756
Address bit configuration for bus write cycles.............................................................................................................766
Write/ erase-protection function....................................................................................................................................771
Security function............................................................................................................................................................771
FCFLCS (Flash control register)...................................................................................................................................773
FCSECBIT(Security bit register)..................................................................................................................................774
"Low" pulse (when the alarm register corresponds with the clock)...........................................................................712
Operation of Boot Program.........................................................................................................................................741
General Boot Program Flowchart...............................................................................................................................755
(1-A) Method 1: Storing a Programming Routine in the Flash Memory
(1-B) Method 2: Transferring a Programming Routine from an External Host
(2-A) Using the Program in the On-Chip Boot ROM
RAM Transfer
Show Flash Memory SUM
Transfer Format for the Show Product Information
Chip Erase and Protect Bit Erase
Block Configuration
Basic Operation
Reset (Hardware reset)
Commands
Flash control / status register
List of Command Sequences
Flowchart
RTCRESTR (Reset register (for PAGE0/1))
RAM Transfer Command
Show Flash Memory SUM Command
Show Product Information Command
Chip and Protection Bit Erase Command
Acknowledge Responses
Determination of a Serial Operation Mode
Password
Calculation of the Show Flash Memory Sum Command
Checksum Calculation