TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 564

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TMPM364F10FG

Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM364F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM364F10FG
Manufacturer:
Toshiba
Quantity:
10 000
Company:
Part Number:
TMPM364F10FG
Quantity:
6 000
16.4
Register
16.4.10
31
30-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
When CANGIF<TRMABF> bit in the global interrupt flag register is also set to "1", and the transmit abort in-
terrupt is enabled by setting the CANGIM<TRAMABM> bit in the global interrupt mask register to "1", the
CAN global interrupt INTCANGB occurs.
write of "0" to the <AAx> bit or the CANTRS<TRSx> bit from the CPU is invalid.
AA30 to AA0
The CANAA<AAx> bit is set to "1" when a message in mailbox x has not been successfully transmitted.
A write of "1" to the <AAx> bit or the CANTRS<TRSx> bit from the CPU can clear the <AAx> bit. A
Bit Symbol
Note:Mailbox 31 is receive-only mailbox.
CANAA (Abort Acknowledge Register)
AA23
AA15
AA7
31
23
15
0
0
0
7
0
-
R
R/W
Type
AA30
AA22
AA14
AA6
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Abort acknowledge (Each bit corresponds with mailboxes 30 to 0.)
When the message in mailbox x has not been successfully transmitted, the <AAx> bit is set to "1".
The <AAx> bit can be cleared by a write of "1" from CPU to the <AAx> bit or the CANTRS<TRSx> bit.
AA29
AA21
AA13
AA5
29
21
13
0
0
0
5
0
Page 538
AA28
AA20
AA12
AA4
28
20
12
0
0
0
4
0
AA27
AA19
AA11
AA3
27
19
11
Function
0
0
0
3
0
AA26
AA18
AA10
AA2
26
18
10
0
0
0
2
0
AA25
AA17
AA9
AA1
25
17
0
0
9
0
1
0
TMPM364F10FG
AA24
AA16
AA8
AA0
24
16
0
0
8
0
0
0

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