TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 15

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

10. Static Memory Controller
11. 16-bit Timer / Event Counters (TMRB)
9.3 Block diagram.......................................................................................................................279
9.4 Description of Registers........................................................................................................280
9.5 Special Functions...................................................................................................................300
10.1 Function Overview..............................................................................................................303
10.2 Block diagram.....................................................................................................................303
10.3 Description of Registers......................................................................................................305
10.4 External Bus Cycle .............................................................................................................319
10.5 Connection example for external memory..........................................................................326
11.1 Outline.................................................................................................................................329
11.2 Differences in the Specifications........................................................................................330
11.3 Configuration.......................................................................................................................332
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
9.4.13
9.4.14
9.4.15
9.4.16
9.4.17
9.5.1
9.5.2
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10
10.3.11
10.3.12
10.3.13
10.3.14
10.4.1
10.4.2
10.4.1.1
10.4.1.2
10.4.1.3
10.4.1.4
10.4.2.1
10.4.2.2
10.4.2.3
DMAC register list..........................................................................................................................................................280
DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................281
DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................282
DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................283
DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................284
DMACIntErrClr (DMAC Interrupt Error Clear Register).............................................................................................285
DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)......................................................286
DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)....................................................................287
DMACEnbldChns (DMAC Enabled Channel Register)................................................................................................288
Scatter/gather function.....................................................................................................................................................300
Linked list operation........................................................................................................................................................301
DMACSoftBReq (DMAC Software Burst Request Register).....................................................................................289
DMACSoftSReq (DMAC Software Single Request Register)....................................................................................291
DMACConfiguration (DMAC Configuration Register)...............................................................................................292
DMACCxSrcAddr (DMAC Channelx Source Address Register)...............................................................................293
DMACCxDestAddr (DMAC Channelx Destination Address Register)......................................................................294
DMACCxLLI (DMAC Channelx Linked List Item Register).....................................................................................295
DMACCxControl (DMAC Channelx Control Register)..............................................................................................296
DMACCxConfiguration (DMAC Channelx Configuration Register)..........................................................................298
SFR List.........................................................................................................................................................................305
SMCMDMODE (Mode Register).................................................................................................................................306
smc_memif_cfg (SMC Memory Interface Configuration Register)............................................................................307
smc_direct_cmd (SMC Direct Command Register).....................................................................................................308
smc_set_cycles (SMC Set Cycles Register).................................................................................................................309
smc_set_opmode (SMC Set Opmode Register)...........................................................................................................310
smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 <0>).....................................................................................311
smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 <1>).....................................................................................312
smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 <2>).....................................................................................313
Separate bus mode.........................................................................................................................................................319
Multiplex mode..............................................................................................................................................................323
smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 <3>)...................................................................................314
smc_opmode0_0 (SMC Opmode Registers 0<0>).....................................................................................................315
smc_opmode0_1 (SMC Opmode Registers 0<1>).....................................................................................................316
smc_opmode0_2 (SMC Opmode Registers 0<2>).....................................................................................................317
smc_opmode0_3 (SMC Opmode Registers 0<3>).....................................................................................................318
tRC / tCEOE setting example
tWC / tWP setting example
tRC / tCEOE / tPC setting example
tTR setting example
tRC / tCEOE setting example
tWC / tWP setting example
tTR setting example
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