TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 472

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13.6
Frame Format
13.6.3
In this mode, when a frame begins, an 8-bit control message is transmitted to the slave. During this transmis-
sion, no incoming data is received by the SSP. After the message has been transmitted, the slave decodes it,
and after waiting one serial clock after the last bit of the 8-bit control message has been sent, it responds
with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length any-
where from 13 to 25 bits.
od for half-duplex communications. Each serial transmission is started by an 8-bit control word, which is
sent to the off-chip slave device. During this transmission, the SSP does not receive input data. After the mes-
sage has been transmitted, the off-chip slave decodes it, and after waiting one serial clock after the last bit of
the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16
bits in length, making the total frame length anywhere from 13 to 25 bits. With this configuration, during the
idle period:
ses the value stored in the bottom entry of the transmit FIFO to be transferred to the serial shift register for
the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SPDO pin.
slave device latches each control bit into its serial shifter on the rising edge of each SPCLK.
and the slave responds by transmitting data back to the SSP. Each bit is driven onto SPDI line on the falling
edge of SPCLK.
fers, the SPFSS signal is pulled "High" one clock period after the last bit has been latched in the receive seri-
al shifter, which causes the data to be transferred to the receive FIFO.
Note 1: When transmission is disabled, SPDO terminal doesn't output and is high impedance status. This terminal
Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance sta-
The Microwire format uses a special master/slave messaging method, which operates in half-duplex mode.
Though the Microwire format is similar to the SPI format, it uses the master/slave message transmission meth-
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SPFSS cau-
SPFSS remains "Low" and the SPDI pin remains tristated during this transmission. The off-chip serial
After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state,
The SSP in turn latches each bit on the rising edge of SPCLK. At the end of the frame, for single trans-
Microwire frame format
・ The SPCLK signal is set to "Low".
・ SPFSS is set to "High".
・ The transmit data line SPDO is set to "Low".
SPFSS
SPDO
SPDI
SPCLK
needs to add suitable pull-up/down resistance to fix the voltage level.
tus, this terminal needs to add suitable pull-up/down resistance to fix the voltage level.
Hi-Z(Note1
Figure 13-6 Microwire frame format (single transfer)
Hi-Z(Note2
MSB
8bit
Page 446
LSB
Hi-Z(Note1
MSB
4 to 16bit
LSB
TMPM364F10FG
Hi-Z(Note2