XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 101

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 65: Slave Serial Mode Connections
DS312-2 (v3.6) May 29, 2007
Product Specification
HSWAP
M[2:0]
DIN
CCLK
INIT_B
DONE
PROG_B
Pin Name
R
FPGA Direction
bidirectional I/O
bidirectional I/O
Open-drain
Open-drain
Input
Input
Input
Input
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank
0: Pull-up during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode. See
Considerations for the HSWAP,
M[2:0], and VS[2:0]
Data Input.
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity. See
CCLK Design
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration.
Requires external 330 Ω pull-up
resistor to 2.5V.
Program FPGA. Active Low.
When asserted Low for 500 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Requires external
4.7 kΩ pull-up resistor to 2.5V. If
driving externally with a 3.3V
output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Description
Considerations.
V
Pins.
CCO
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Design
input.
Drive at valid logic level
throughout configuration.
M2 = 1, M1 = 1, M0 = 1 Sampled
when INIT_B goes High.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
External clock.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
Low indicates that the FPGA is
not yet configured.
Must be High to allow
configuration to start.
During Configuration
User I/O
User I/O
User I/O
User I/O
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA.
Functional Description
After Configuration
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