XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 63

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Quadrant Clock Routing
The clock routing within the FPGA is quadrant-based, as
shown in
total clock signals, labeled ‘A’ through ‘H’ in
Figure
inates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along
the associated edge, as shown in
feed the synchronous resource elements (CLBs, IOBs,
block RAM, multipliers, and DCMs) within the quadrant.
DS312-2 (v3.6) May 29, 2007
Product Specification
47. The clock source for an individual clock line orig-
Figure
R
45. Each clock quadrant supports eight
*(XC3S1200E and
RHCLK input
Double Line
XC3S1600E only)
DCM output*
LHCLK or
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
CLK Switch
Figure
Left-/Right-Half BUFGMUX
Matrix
47. The clock lines
Table 41
S
S
I0
I1
I0
I1
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0
1
0
1
and
BUFGMUX
O
O
2nd DCM output
1st DCM output
2nd GCLK pin
1st GCLK pin
Double Line
The four quadrants of the device are:
•
•
•
•
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement con-
straints.
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
S
S
I0
I1
I0
I1
0
1
0
1
DS312-2_16_110706
Functional Description
BUFGMUX
O
O
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