XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 177

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

User I/Os by Bank
Table 133
tributed on the XC3S100E FPGA packaged in the CP132
package.
Table 133: User I/Os Per Bank for the XC3S100E in the CP132 Package
Table 134: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
DS312-4 (v3.6) May 29, 2007
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
Table 134
shows how the 83 available user-I/O pins are dis-
R
I/O Bank
I/O Bank
indicates how the 92 available user-I/O
0
1
2
3
0
1
2
3
Maximum
Maximum
I/O
I/O
18
23
22
20
83
22
23
26
21
92
I/O
I/O
10
16
22
11
11
6
0
0
0
0
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pins are distributed on the XC3S250E and the XC3S500E
FPGAs in the CP132 package.
INPUT
INPUT
2
0
0
0
2
0
0
0
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
21
20
42
21
24
46
1
0
1
0
VREF
VREF
1
2
2
2
7
2
2
2
2
8
Pinout Descriptions
(1)
(1)
CLK
CLK
0
0
0
0
16
16
8
8
8
8
(2)
(2)
(2)
(2)
(1)
(1)
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