XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 71

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 46: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
The HSWAP pin itself has an pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All
other configuration pins are dual-purpose I/O pins and are
available to the FPGA application after the DONE pin goes
High. See
Table 46
ious configuration pins during the configuration process.
The configuration interface is designed primarily for 2.5V
operation when the VCCO_2 (and VCCO_1 in BPI mode)
connects to 2.5V.
The configuration pins also operate at other voltages by set-
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the V
drive characteristics. For example, with V
output current when driving High, I
imately 12 to 16 mA, while the current when driving Low,
I
driving High, I
mA. Again, the current when driving Low, I
8 mA.
CCLK Design Considerations
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
The FPGA’s configuration process is controlled by the
CCLK configuration clock. Consequently, signal integrity of
CCLK is important to guarantee successful configuration.
Poor CCLK signal integrity caused by ringing or reflections
might cause double-clocking, causing the configuration pro-
cess to fail.
Although the CCLK frequency is relatively low, Spartan-3E
FPGA output edge rates are fast. Therefore, careful atten-
tion must be paid to the CCLK signal integrity on the printed
circuit board. Signal integrity simulation with IBIS is recom-
mended. For all configuration modes except JTAG, the sig-
nal integrity must be considered at every CCLK trace
destination, including the FPGA’s CCLK pin.
This analysis is especially important when the FPGA
re-uses the CCLK pin as a user-I/O after configuration. In
these cases, there might be unrelated devices attached to
DS312-2 (v3.6) May 29, 2007
Product Specification
OL
All, including CCLK
, remains 8 mA. At V
Pin(s)
shows the default I/O standard setting for the var-
Start-Up
R
OH
, decreases slightly to approximately 6 to 8
for additional information.
CCO
I/O Standard
CCO
LVCMOS25
= 1.8V, the output current when
supply also changes the I/O
OH
, increases to approx-
CCO
Output Drive
OL
= 3.3V, the
, remains
8 mA
www.xilinx.com
CCLK, which add additional trace length and signal destina-
tions.
In the Master Serial, SPI, and BPI configuration modes, the
FPGA drives the CCLK pin and CCLK should be treated as
a full bidirectional I/O pin for signal integrity analysis. In BPI
mode, CCLK is only used in multi-FPGA daisy-chains.
The best signal integrity is ensured by following these basic
PCB guidelines:
•
•
•
•
Design Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Unlike previous Spartan FPGA families, nearly all of the
Spartan-3E dual-purpose configuration pins are available
as full-featured user I/O pins after successful configuration,
when the DONE output goes High.
The HSWAP pin, the mode select pins (M[2:0]), and the
variant-select pins (VS[2:0]) must have valid and stable
logic values at the start of configuration. VS[2:0] are only
used in the SPI configuration mode. The levels on the
M[2:0] pins and VS[2:0] pins are sampled when the INIT_B
pin returns High. See
The HSWAP pin defines whether FPGA user I/O pins have
a pull-up resistor connected to their associated V
ply pin during configuration or not, as shown
HSWAP must be valid at the start of configuration and
remain constant throughout the configuration process.
Table 47: HSWAP Behavior
HSWAP
Value
Route the CCLK signal as a 50
controlled-impedance transmission line.
Route the CCLK signal without any branching. Do not
use a “star” topology.
Keep stubs, if required, shorter than 10 mm (0.4
inches).
Terminate the end of the CCLK transmission line.
0
1
Pull-up resistors connect to the associated
V
I/O pins during configuration. Pull-up resistors
are active until configuration completes.
Pull-up resistors disabled during configuration.
All user-I/O or dual-purpose I/O pins are in a
high-impedance state.
CCO
supply for all user-I/O or dual-purpose
Figure 77
Slew Rate
Slow
Description
for a timing example.
Functional Description
Ω
CCO
Table
sup-
47.
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