XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 32

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
The MULT_AND is useful for small multipliers. Larger multi-
pliers can be built using the dedicated 18x18 multiplier
blocks (see
Storage Elements
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch, pro-
vides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and bot-
Table 15: Storage Element Signals
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
Initialization
The CLB storage elements are initialized at power-up, dur-
32
Figure 25: FD Flip-Flop Component with Synchronous
D
Q
C
G
CE
GE
S
R
PRE
CLR
SR
REV
Signal
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High
during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate
enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low
gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or
GE remains Low.
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
Clock for edge-triggered flip-flops.
Gate for level-sensitive latches.
Clock Enable for flip-flops.
Gate Enable for latches.
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
Synchronous Reset (Q = Low); has precedence over Set.
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High,
during the Low-to-High clock (C) transition. A latch output is immediately set, output High.
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
CLB input for R, S, CLR, or PRE
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
Dedicated
Reset, Set, and Clock Enable
CE
D
C
R
S
Multipliers).
FDRSE
DS312-2_40_021305
Q
www.xilinx.com
Description
tom portions of the slice are called FFY and FFX, respec-
tively. FFY has a fixed multiplexer on the D input selecting
either the combinatorial output Y or the bypass signal BY.
FFX selects between the combinatorial output X or the
bypass signal BX.
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All sig-
nals have programmable polarity; the default active-High
function is described.
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
ing configuration, by the global GSR signal, and by the indi-
vidual SR or REV inputs to the CLB. The storage elements
can also be re-initialized using the GSR input on the
R
1
0
0
0
0
S
X
1
0
0
0
Inputs
CE
X
X
0
1
1
D
X
X
X
1
0
DS312-2 (v3.6) May 29, 2007
C
↑
↑
X
↑
↑
Product Specification
No Change
Outputs
Q
0
1
1
0
R