XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 105

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

VCCO_2
VCCINT
VCCAUX
PROG_B
CCLK
TCK
M1
M2
Option
Option
Power On Reset (POR)
V
V
V
CCO2T
CCINTT
CCAUXT
= Bitstream Generator (BitGen) Option
= Design Attribute
1
0
Glitch Filter
ConfigRate
Oscillator
Internal
POWER_GOOD
1
0
ENABLE
INTERNAL_CONFIGURATION_CLOCK
INITIALIZATION
Clear internal CMOS
configuration latches
CLEARING_MEMORY
RESET
STARTUP_WAIT=TRUE
DCM in User
JTAG_CLOCK
Application
WAIT
DONE
LOCKED
CRC
CONFIGURATION
ENABLE
USER_CLOCK
configuration latches
Load application
data into CMOS
RESET
All DCMs
ENABLE
Configuration Error
(CRC Checker)
Detection
DONE
*
StartupClk
ERROR
USER
USER
*
*
DCMs_LOCKED
ENABLE
GTS_IN
GSR_IN
Enable application logic and
*
LCK_cycle
RESET
DriveDone
These connections are available via the
STARTUP_SPARTAN3E library primitive.
STARTUP
I/O pins
WAIT
DonePipe
DONE
GWE
GSR
GTS
DONE_cycle
GWE_cycle
GTS_cycle
EN
EN
Force all I/Os Hi-Z
Hold all storage
elements reset
Disable write
operations to
storage elements
INIT_B
DONE