XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 42

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Table 25: Block RAM Function Table (Continued)
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
Table 26: WRITE_MODE Effect on Data Output Latches During Write Operations
42
GSR
WRITE_FIRST
Read After Write
READ_FIRST
Read Before Write
NO_CHANGE
No Read on Write
0
Write Mode
EN
1
SSR
0
Input Signals
WE
Data on DI and DIP inputs is written into
specified RAM location and simultaneously
appears on DO and DOP outputs.
Data from specified RAM location appears on
DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
Data on DO and DOP outputs remains
unchanged.
Data on DI and DIP inputs is written into
specified location.
1
CLK
↑
Effect on Same Port
ADDR
Write RAM, Simultaneous Read Operation
addr
pdata
DIP
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Data
DI
RAM(data)
portions of
which WE is Low.
Data also can be accessed on the DO outputs when assert-
ing the WE input based on the value of the
attribute as described in
No Chg
pdata
DOP
Output Signals
Invalidates data on DO and DOP outputs.
Data from specified RAM location appears on
DO and DOP outputs.
Invalidates data on DO and DOP outputs.
WRITE_MODE = WRITE_FIRST
WRITE_MODE = NO_CHANGE
WRITE_MODE = READ_FIRST
Figure
RAM(data)
(dual-port only with same address)
No Chg
data
DO
33,
Effect on Opposite Port
Figure
Table
RAM(addr)
RAM(addr)
RAM(addr)
26.
← pdata
← pdata
← pdata
34, and
DS312-2 (v3.6) May 29, 2007
Parity
RAM Data
Product Specification
Figure 35
WRITE_MODE
RAM(addr)
RAM(addr)
RAM(addr)
← pdata
← pdata
← data
Data
during
R