XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 45

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Dedicated Multipliers
For additional information, refer to the “Using Embedded
Multipliers” chapter in UG331.
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See
details on the location of these blocks and their connectivity.
Operation
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications, such as simple data storage and bar-
rel shifting. Logic slices also implement efficient small multi-
pliers and thereby supplement the dedicated multipliers.
The Spartan-3E dedicated multiplier blocks have additional
features beyond those provided in Spartan-3 FPGAs.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values rang-
ing from -131,072
ranging from -17,179,738,112
Use the
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a multi-
plier, adding the pipeline registers may require the
MULT18X18SIO primitive. Connect the appropriate signals
DS312-2 (v3.6) May 29, 2007
Product Specification
MULT18X18SIO
R
Arrangement of RAM Blocks on Die
10
to +131,071
Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks
A[17:0]
B[17:0]
primitive shown in
RSTB
RSTA
CEA
CEB
CLK
10
to +17,179,869,184
10
with a resulting product
CE
D
CE
D
(Optional)
(Optional)
AREG
BREG
RST
RST
Figure 37
Q
Q
10
www.xilinx.com
.
for
to
X
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the most-signifi-
cant bit). Wider multiplication operations are performed by
combining the dedicated multipliers and slice-based logic in
any viable combination or by time-sharing a single multi-
plier. Perform unsigned multiplication by restricting the
inputs to the positive range. Tie the most-significant bit Low
and represent the unsigned value in the remaining 17
lesser-significant bits.
Optional Pipeline Registers
As shown in
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an inde-
pendent clock enable and synchronous reset controls mak-
ing them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Figure 36
block.
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the asso-
ciated register, or to 0 to remove it and make the signal path
combinatorial.
RSTP
CEP
illustrates the principle features of the multiplier
CE
D
Figure
(Optional)
PREG
RST
Q
36, each multiplier block has optional
DS312-2_27_021205
P[35:0]
Functional Description
45