XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 109

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain,
forcing the FPGAs to start synchronously. Similarly, the
start-up sequence can be paused at any stage, waiting for
selected DCMs to lock to their respective input clock sig-
nals. See also
Mode.
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the
setting the
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For
JTAG configuration, the start-up sequence can be synchro-
nized to the TCK clock input.
Readback
FPGA configuration data can be read back using either the
Slave Parallel or JTAG mode. This function is disabled if the
Bitstream Generator
or Level2.
Along with the configuration data, it is possible to read back
the contents of all registers and distributed RAM.
To synchronously control when register values are captured
for readback, use the
tive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
The Readback feature is available in most Spartan-3E
FPGA product options, as indicated in
DS312-2 (v3.6) May 29, 2007
Product Specification
STARTUP_SPARTAN3E
R
StartupClk
Stabilizing DCM Clocks Before User
Security
CAPTURE_SPARTAN3
bitstream generator option. The
option is set to either Level1
library primitive and by
Table
67. The Read-
library primi-
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back feature is not available in the XC3S1200E and
XC3S1600E FPGAs when using the -4 speed grade in the
Commercial temperature grade. Similarly, block RAM
Readback support is not available in the -4 speed grade,
Commercial temperature devices. If Readback is required
in an XC3S1200E or XC3S1600E FPGA, or if block RAM
Readback is required on any Spartan-3E FPGA, upgrade to
either the Industrial temperature grade version or the -5
speed grade.
The Xilinx iMPACT programming software uses the Read-
back feature for its optional Verify and Readback opera-
tions. The Xilinx ChipScope™ software presently does not
use Readback but may in future updates.
Table 67: Readback Support in Spartan-3E FPGAs
Block RAM Readback
General Readback (registers, distributed RAM)
Temperature Range
All Spartan-3E
Speed Grade
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
FPGAs
Yes
Yes
Yes
No
No
No
-4
Commercial
Functional Description
Yes
Yes
Yes
Yes
Yes
Yes
-5
Industrial
Yes
Yes
Yes
Yes
Yes
Yes
-4
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