XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 155

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 116: Timing for the Slave Parallel Configuration Mode (Continued)
DS312-3 (v3.6) May 29, 2007
Product Specification
Notes:
1.
2.
3.
Hold Times
T
T
T
Clock Timing
T
T
F
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
The numbers in this table are based on the operating conditions set forth in
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
R
The time from the active edge of the CCLK pin to the point when data is last
held at the D0-D7 pins
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the CSO_B pin
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
With bitstream compression
Description
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Table
76.
DC and Switching Characteristics
(2)
All Speed Grades
Min
1.0
0
0
5
5
0
0
0
Max
50
66
20
-
-
-
-
-
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
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