XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 87

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

determines how the FPGA generates addresses, as shown
Table
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
DS312-2 (v3.6) May 29, 2007
Product Specification
A
During configuration, the value of the M0 mode pin
57. When M0 = 0, the FPGA generates addresses
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
R
Recommend
open-drain
PROG_B
driver
TMS
TDO
TCK
TDI
+2.5V
JTAG
Not available
in VQ100
package
BPI Mode
‘0’
‘1’
‘0’
‘0’
P
A
HSWAP
M2
M1
M0
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Spartan-3E
FPGA
VCCINT
+1.2V
GND
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VCCAUX
VCCO_1
VCCO_0
VCCO_2
A[23:17]
CSO_B
A[16:0]
INIT_B
DONE
BUSY
CCLK
LDC0
LDC1
LDC2
D[7:0]
HDC
TDO
Table 57: BPI Addressing Control
M2
0
VCCO_0
+2.5V
M1
V
V
1
V
M0
0
1
I
Start Address
0xFF_FFFF
CE#
OE#
WE#
BYTE#
DQ[15:7]
DQ[7:0]
A[n:0]
0
DS312-2_49_103105
VCCO
GND
Functional Description
V
x8/x16
PROM
Flash
+2.5V
x8 or
D
Incrementing
Decrementing
Addressing
87