MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet - Page 19

• Manufacturer Part Number: MT9VDDT6472HY-40B
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
22. The data valid window is derived by achieving
23. This limit is actually a nominal value and does not
24. To maintain a valid level, the transitioning edge of
25. JEDEC specifies CK and CK# input slew rate must
26. DQ and DM input slew rates must not deviate
27. V
28. The clock is allowed up to ±150ps of jitter. Each
29.
30. READs and WRITEs with auto precharge are not
31. Any positive glitch in the nominal voltage must be
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Each byte lane has a corresponding
DQS.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
be ≥ 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain. For -40B, slew rates must be ≥ 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+300mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
t
QH =
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
V
IH
must not vary more than 4 percent if CKE is
(
t
IH
DC
HP -
(
).
AC
t
).
QHS). The data valid window derates
t
HP (
t
t
t
CK/2),
CL minimum and
RAS(MIN) can be satis-
t
RFC [MIN]) else
t
DQSQ, and
IL
t
DS and
(
DC
IL
t
(
t
QH
) or
CH
AC
)
256MB, 512MB, 1GB (x72, ECC, SR)
19
32. Normal Output Drive Curves:
33. The voltage levels used are derived from a mini-
34. V
35. V
36.
37.
cycle and not exceed either 2.4V minimum,
whichever is more positive.
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
8, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V,
and at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width ≤ 3ns and the
overshoot: V
and V
t
DQSCK (MIN) +
DD
DD
level and the referenced test load. In
200-PIN DDR SODIMM
Q must track each other.
IH
(MAX) = V
t
RPRE (MAX) condition.
t
RPRE begin point are not
©2005 Micron Technology, Inc. All rights reserved.
t
t
LZ (MIN) will prevail
RPRE).
t
DD
DQSCK (MAX) +
Q + 1.5V for a
IL
undershoot: