MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet - Page 4

• Manufacturer Part Number: MT9VDDT6472HY-40B
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
11, 25, 47, 61, 77, 133, 147,
12, 26, 48, 62, 78, 134, 148,
139-142, 145-146, 151-154,
163-166, 171-172, 175-178,
41-44, 49-50, 53-56, 59-60,
65-68, 127-130, 135-136,
111, 112, 115, 123
5-8, 13-20, 23-24, 29-32,
106, 107, 108, 109, 110,
35, 37, 89, 91, 158, 160
99, 100, 101, 102, 105,
181-182, 187-190
71,72, 73, 74, 79,
PIN NUMBERS
118, 119, 120
80, 83, 84
116, 117
169, 183
170, 184
121
96
Pin Descriptions
(1GB)
WE#, CAS#, RAS#
CK1#, CK2, CK2#
(256MB, 512MB)
CK0, CK0#, CK1,
DQS0–DQS8
DQ0–DQ63
DM0–DM8
SYMBOL
BA0, BA1
CB0–CB7
A0–A12
A0–A13
(1GB)
CKE0
S0#
Output
Output
Output
Input/
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also
provide the op-code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register (mode register or
extended mode register) is loaded during the LOAD MODE
REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Check Bits.
Data I/Os: Data bus.
256MB, 512MB, 1GB (x72, ECC, SR)
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
200-PIN DDR SODIMM
DESCRIPTION
©2005 Micron Technology, Inc. All rights reserved.
DD
is applied.