MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet - Page 9

• Manufacturer Part Number: MT9VDDT6472HY-40B
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Table 6:
NOTE:
Table 7:
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
LENGTH
1. For a burst length of two, A1–Ai select the two-data-
2. For a burst length of four, A2–Ai select the four-data-
3. For a burst length of eight, A3–Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9 for 256MB;
BURST
SPEED
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
element block; A0–A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 for 512MB, 1GB.
-40B
2
4
8
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
75 ≤ f ≤ 133
Burst Definition Table
CAS Latency (CL) Table
CL = 2
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
CLOCK FREQUENCY (MHZ)
A0
ALLOWABLE OPERATING
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
75 ≤ f ≤ 167
CL = 2.5
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
A BURST
INTERLEAVED
125 ≤ f ≤ 200
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
256MB, 512MB, 1GB (x72, ECC, SR)
9
Operating Mode
MODE REGISTER SET command with bits A7–A12
(256MB, 512MB) or A7–A13 (1GB) each set to zero, and
bits A0–A6 set to the desired values. A DLL reset is ini-
tiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A12 (256MB, 512MB) or A7 and A9–
A13 (1GB) each set to zero, bit A8 set to one, and bits
A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recom-
mend when a LOAD MODE REGISTER command is
issued to reset the DLL, it should always be followed by
a LOAD MODE REGISTER command to select normal
operating mode.
512MB) or A7–A13 (1GB) are reserved for future use
and/or test modes. Test modes and reserved states
should not be used because unknown operation or
incompatibility with future versions may result.
COMMAND
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7–A12 (256MB,
DQS
DQS
DQS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
T0
200-PIN DDR SODIMM
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
©2005 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
NOP
T2
T2
T2n
T2n
T2n
DON’T CARE
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n