MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet - Page 20

• Manufacturer Part Number: MT9VDDT6472HY-40B
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
38. During initialization, V
39. The current Micron part operates below the slow-
40. Random addressing changing and 50 percent of
41. Random addressing changing and 100 percent of
42. CKE must be active (high) during the entire time a
160
140
120
100
80
60
40
20
Figure 7: Pull-Down Characteristics
0
0.0
be equal to or less than V
V
even if V
42Ω of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
TT
may be 1.35V maximum during power up,
DD
0.5
/V
DD
Q are 0V, provided a minimum of
1.0
V
V
OUT
OUT
DD
(V)
(V)
DD
Q, V
1.5
+ 0.3V. Alternatively,
TT
, and V
2.0
Minimum
REF
must
TT
2.5
256MB, 512MB, 1GB (x72, ECC, SR)
20
43. I
44. Whenever the operating frequency is altered, not
45. Leakage number reflects the worst case leakage
46. When an input signal is HIGH or LOW, it is
47. This is the DC voltage supplied at the DDR
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
SDRAM device and is inclusive of all noise up to
20 MHz. Any noise above 20 MHz at the DDR
SDRAM device generated from any source other
than the device itself may not exceed the DC volt-
age range of +2.6V ±0.1V.
Figure 8: Pull-Up Characteristics
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2N specifies the DQ, DQS, and DM to be
2F is “worst case.”
0.5
DD
200-PIN DDR SODIMM
DD
2F, I
2F except I
DD
1.0
V
DD
2N, and I
Q - V
©2005 Micron Technology, Inc. All rights reserved.
OUT
(V)
1.5
DD
DD
2Q specifies the
2Q are similar,
2.0
DD
2Q is
2.5