MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet - Page 8

• Manufacturer Part Number: MT9VDDT6472HY-40B
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Burst Length
burst oriented, with the burst length being program-
mable, as shown in Mode Register Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2, or 2.5 clocks, as shown in Figure 5,
CAS Latency Diagram, on page 9.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
Read and write accesses to DDR SDRAM devices are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
256MB, 512MB, 1GB (x72, ECC, SR)
8
operation or incompatibility with future versions may
result.
256MB and 512MB Modules
* M15 and M14 (BA1 and BA0)
* M14 and M13 (BA0 and BA1) must be “0, 0” to select the
1GB Module
0*
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
base mode register (vs. the extended mode register).
BA1
15
Reserved states should not be used as unknown
Figure 4: Mode Register Definition
0*
0*
14
BA1
BA0
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
13
BA0
13
A13
12
A12 A11
12
A12 A11
Operating Mode
Operating Mode
11
11
M13
0
0
-
10
10
A10
A10
M12 M11
0
0
-
9
9
200-PIN DDR SODIMM
A9
A9
0
0
-
8
A8
8
A8
M10
0
0
-
Diagram
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
CAS Latency BT
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
5
0
0
-
M4
©2005 Micron Technology, Inc. All rights reserved.
0
1
0
1
0
1
0
1
4
4
M6-M0
M3
0
1
Valid
Valid
3
3
-
Burst Length
Burst Length
M2
2
2
0
0
0
0
1
1
1
1
A2 A1 A0
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
3
M0
0
1
0
1
0
1
0
1
0
0
Interleaved
Burst Type
Sequential
Burst Length
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
2
4
8