upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 176

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

9.4 Operation of Watchdog Timer
9.4.1 Watchdog timer operation when “Internal oscillator cannot be stopped” is selected by option byte
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
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The operation clock of watchdog timer is fixed to the internal oscillation clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
The status after reset release is as follows.
• Operation clock: Internal oscillation clock
• Cycle: 2
• Counting starts
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
2.
instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation clock can
be selected as the count source, so after STOP instruction execution, clear the watchdog timer
using the interrupt request of TMH1 before the watchdog timer overflows. If this processing is
not performed, an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
The operation clock (internal oscillation clock) cannot be changed. If any value is written to bits 3 and
4 (WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1, 2
18
/f
R
.
(546.13 ms: At operation with f
CHAPTER 9 WATCHDOG TIMER
User’s Manual U16846EJ3V0UD
R
= 480 kHz (MAX.))