upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 432

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

432
Standby
function
Reset function
Clock monitor
Power-on-
clear circuit
(POC)
Low-voltage
detector (LVI)
Function
Details of Function
STOP mode
setting and
operating statuses
Reset timing due
to watchdog timer
overflow
RESF: Reset
control flag
register
CLM: Clock
monitor mode
register
Operation of clock
monitor
Functions of
power-on-clear
circuit
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-voltage
detection level
selection register
When used as
reset
−
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT
mode immediately after execution of the STOP instruction and the system returns to the
operating mode as soon as the wait time set using the oscillation stabilization time select
register (OSTS) has elapsed.
For an external reset, input a low level for 10
During reset input, the high-speed system clock and the internal oscillation clock stop
oscillating.
When the STOP mode is released by a reset, the STOP mode contents are held during
reset input. However, the port pins become high-impedance, except for P130, which is set
to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data via a 1-bit memory manipulation instruction.
Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the
internal reset signal.
If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1
(CLMRF) of the reset control flag register (RESF) is set to 1.
Waiting for the oscillation stabilization time is not required when the external RC oscillation
clock is selected as the high-speed system clock by the option byte. Therefore, the CPU
clock can be switched without reading the OSTC value. However, the clock monitor starts
operation after the oscillation stabilization time (OSTS register reset value = 05H (2
has elapsed.
If an internal reset signal is generated in the POC circuit, the reset control flag register
(RESF) is cleared to 00H.
The supply voltage is V
sure to use the standard products and (A) grade products in a voltage range of 2.2 to 5.5 V
because the detection voltage (V
The supply voltage is V
sure to use the (A1) grade products in a voltage range of 2.25 to 5.5 V because the
detection voltage (V
In a system where the supply voltage (V
the POC detection voltage (V
the reset status. In this case, the time from release of reset to the start of the operation of
the microcontroller can be arbitrarily set by taking the following action.
To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Be sure to clear bits 4 to 7 to 0.
Clear all port pins after the supply voltage (V
after POC release in the (A1) grade products.
<1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after
the processing in <3>.
If supply voltage (V
signal is not generated.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
DD
POC
) ≥ detection voltage (V
) of the POC circuit is 2.0 to 2.25 V.
DD
DD
= 2.0 to 5.5 V when the internal oscillation clock is used, but be
= 2.0 to 5.5 V when the internal oscillation clock is used, but be
POC
), the system may be repeatedly reset and released from
POC
) of the POC circuit is 2.1 V ±0.1 V.
DD
Cautions
) fluctuates for a certain period in the vicinity of
LVI
DD
µ
) when LVIMD is set to 1, an internal reset
) exceeds the preset detection voltage (V
s or more to the RESET pin.
16
/f
XP
))
LVI
)
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p. 302
p. 302
p. 302
p. 303
p. 304
p. 308
p. 310
p. 310
pp. 312,
313
p. 316
p. 316
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p. 322
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