upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 431

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Interrupt
Standby
function
Function
Details of Function
MK1L: Interrupt
mask flag register
PR1L: Priority
specification flag
register
EGP, EGN:
External interrupt
rising, falling edge
enable registers
Software interrupt
request
acknowledgment
Interrupt request
hold
STOP mode,
HALT mode
STOP mode
OSTC: Oscillation
stabilization time
counter status
register
OSTS: Oscillation
stabilization time
select register
−
Be sure to set bits 2 to 7 of MK1L to 1.
Be sure to set bits 2 to 7 of PR1L to 1.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected
when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes the IE
flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during
execution of the BRK instruction, the interrupt request is not acknowledged.
The RSTOP setting is valid only when “Can be stopped by software” is set for the internal
oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of
the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then
execute the HALT or STOP instruction.
If the internal oscillator is operating before the STOP mode is set, oscillation of the internal
oscillation clock cannot be stopped in the STOP mode. However, when the internal
oscillation clock is used as the CPU clock, CPU operation is stopped for 17/f
STOP mode is released.
Waiting for the oscillation stabilization time is not required when the external RC oscillation
clock is selected as the high-speed system clock by the option byte. Therefore, the CPU
clock can be switched without reading the OSTC value.
After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 293
If the STOP mode is entered and then released while the internal oscillation clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
The oscillation stabilization time counter counts only during the oscillation stabilization time
set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time
set by OSTS are set to OSTC after STOP mode has been released.
The wait time when STOP mode is released does not include the time after STOP mode
release until clock oscillation starts (“a” below) regardless of whether STOP mode is
released by RESET input or interrupt generation.
To set the STOP mode when the high-speed system clock is used as the CPU clock, set
OSTS before executing a STOP instruction.
Execute the OSTS setting after confirming that the oscillation stabilization time has elapsed
as expected in the OSTC.
If the STOP mode is entered and then released while the internal oscillation clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
The oscillation stabilization time counter counts only during the oscillation stabilization time
set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time
set by OSTS are set to OSTC after STOP mode has been released.
The wait time when STOP mode is released does not include the time after STOP mode
release until clock oscillation starts (“a” below) regardless of whether STOP mode is
released by RESET input or interrupt generation.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
Cautions
R
(s) after
p. 280
p. 281
p. 282
p. 286
p. 290
p. 291
p. 292
p. 292
p. 292
p. 293
p. 293
p. 293
p. 294
p. 294
p. 294
p. 294
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