upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 430

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

430
Serial
interface
UART6
Serial
interface
CSI10
Interrupt
Function
Details of Function
Normal reception
Generation of
serial clock
Permissible baud
rate range during
reception
SOTB10:
Transmit buffer
register 10
SIO10: Serial I/O
shift register 10
CSIM10: Serial
operation mode
register 10
CSIC10: Serial
clock selection
register 10
3-wire serial I/O
mode
Communication
operation
SO10 output
IF1L: Interrupt
request flag
register
IF0L, IF0H, IF1L:
Interrupt request
flag registers
Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
Reception is always performed with the “number of stop bits = 1”. The second stop bit is
ignored.
Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Do not access SOTB10 when CSOT10 = 1 (during serial communication).
Do not access SIO10 when CSOT10 = 1 (during serial communication).
Be sure to clear bit 5 to 0.
When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of
the internal oscillator is divided and supplied as the serial clock. At this time, the operation
of serial interface CSI10 is not guaranteed.
Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
To use P10/SCK10(/TxD0), P11/SI10(/RxD0), and P12/SO10 as general-purpose ports, set
CSIC10 in the default status (00H).
The phase type of the data clock is type 1 after reset.
Take relationship with the other party of communication when setting the port mode register
and port register.
Do not access the control register and data register when CSOT10 = 1 (during serial
communication).
If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.
Be sure to set bits 2 to 7 of IF1L to 0.
When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the
interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and
“_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly
instructions after compilation must be 1-bit memory manipulation instructions (CLR1).
If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C language, for
example, it is converted to the following three assembly instructions after compilation:
mov
and
mov
In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request flag of
another bit of the identical interrupt request flag register is set to 1, it is cleared to 0 by “mov
IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
APPENDIX D LIST OF CAUTIONS
a, IF0L
a, #0FEH
IF0L, a
User’s Manual U16846EJ3V0UD
Cautions
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