upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 426

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

426
A/D converter
Function
Details of Function
Conflicting
operations
Noise
countermeasures
ANI0/P20 to
ANI3/P23
Input impedance
of ANI0 to ANI3
pins
AV
impedance
Interrupt request
flag (ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR) read
operation
A/D converter
sampling time and
A/D conversion
start delay time
REF
pin input
Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction
upon the end of conversion
ADCR read has priority. After the read operation, the new conversion result is written to
ADCR.
Conflict between ADCR write and A/D converter mode register (ADM) write or analog input
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
To maintain the 10-bit resolution, attention must be paid to noise input to the AV
ANI0 to ANI3 pins. Because the effect increases in proportion to the output impedance of
the analog input source, it is recommended that a capacitor be connected externally, as
shown in Figure 10-19, to reduce noise.
The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2
while conversion is in progress; otherwise the conversion resolution may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently being used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to coupling
noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D
conversion.
In this A/D converter, the internal sampling capacitor is charged and sampling is performed
for approx. one sixth of the conversion time.
Since only the leakage current flows other than during sampling and the current for
charging the capacitor also flows during sampling, the input impedance fluctuates and has
no meaning.
To perform sufficient sampling, however, it is recommended to make the output impedance
of the analog input source 10 kΩ or lower, or attach a capacitor of around 100 pF to the
ANI0 to ANI3 pins (see Figure 10-19).
A series resistor string of several tens of kΩ is connected between the AV
Therefore, if the output impedance of the reference voltage source is high, this will result in
a series connection to the series resistor string between the AV
in a large reference voltage error.
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion
result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Caution is therefore required since, at this time, when ADIF is read immediately after the
ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input
has not finished.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion
operation is resumed.
The first A/D conversion value immediately after A/D conversion starts may not fall within
the rating range if the ADCS bit is set to 1 within 14
the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D
conversion end interrupt request (INTAD) and removing the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM) and analog
input channel specification register (ADS), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM and
ADS. Using a timing other than the above may cause an incorrect conversion result to be
read.
The A/D converter sampling time differs depending on the set value of the A/D converter
mode register (ADM). A delay time exists until actual sampling is started after A/D
converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is
required regarding the contents shown in Figure 10-21 and Table 10-3.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
Cautions
µ
s after the ADCE bit was set to 1, or if
REF
and AV
REF
SS
pins, resulting
and AV
REF
and
SS
pins.
p. 196
p. 196
p. 197
p. 197
p. 197
p. 197
p. 197
p. 198
p. 198
p. 198
p. 199
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