ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 112

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: 2kHz/8kHz Source (2K8KSRC). This configuration bit specifies the source for the 2kHz and 8kHz outputs
available on clock outputs. When MCR4:LKT4T0 = 1 it is always connected to the T0 DPLL. See Section 7.8.2.3.
Bit 6 to 4: SYNC123 Source (SYNCSRC). This field determines whether the SYNC1, SYNC2, or SYNC3 pins are
associated with the selected input clock or forced to be associated with a specific input clock. See Section 7.9.3.
Bit 3: 8kHz Invert (8KINV). When this bit is set to 1 the 8kHz signal on clock output FSYNC is inverted. See
Section 7.8.2.4.
Bit 2: 8kHz Pulse (8KPUL). When this bit is set to 1, the 8kHz signal on clock output FSYNC is pulsed rather than
50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the
clock period of OC3. See Section 7.8.2.4.
Bit 1: 2kHz Invert (2KINV). When this bit is set to 1 the 2kHz signal on clock output MFSYNC is inverted. See
Section 7.8.2.4.
Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather
than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to
the clock period of OC3. See Section 7.8.2.4.
________________________________________________________________________________________ DS3104-SE
0 = T0 DPLL
1 = T4 DPLL
0XX = SYNC[1:3] pins associated with T0 DPLL selected reference IC3 or IC5, IC4 or IC6, IC9, or IC2
1X0 = SYNC1 pin associated with IC3, SYNC2 pin associated with IC4
1X1 = SYNC1 pin associated with IC5, SYNC2 pin associated with IC6
10X = SYNC3 pin associated with IC9
11X = SYNC3 pin associated with IC2
0 = FSYNC not inverted
1 = FSYNC inverted
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
0 = MFSYNC not inverted
1 = MFSYNC inverted
0 = MFSYNC not pulsed; 50% duty cycle
1 = MFSYNC pulsed, with pulse width equal to OC3 period
2K8KSRC
Bit 7
0
Bit 6
0
FSCR1
Frame Sync Configuration Register 1
7Ah
SYNCSRC[2:0]
Bit 5
0
Bit 4
0
8KINV
Bit 3
0
8KPUL
Bit 2
0
2KINV
Bit 1
0
2KPUL
Bit 0
0
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