ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 39

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8.2.3 OC1 to OC7 Configuration
The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 through OC7:
Table 7-14
the T4 APLL to obtain each frequency.
Table 7-7. Digital1 Frequencies
Table 7-8. Digital2 Frequencies
________________________________________________________________________________________ DS3104-SE
SETTING
IN
DIG2AF
SETTING IN
DIG1F[1:0]
MCR6
1
1
1
1
0
0
0
0
0
0
0
0
MCR7
1) Determine whether the T4 APLL must be independent of the T0 DPLL or not. If the T4 APLL
2) Use
3) Determine from
4) Configure the T0FREQ field in register
5) Using
00
01
10
11
00
01
10
11
lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or
must be independent, set T4APT0 = 0 in register T0CR1. If the T4 APLL must be locked to the
T0 DPLL then set T4APT0 = 1.
only generate one set of output frequencies. (In SONET/SDH equipment the T0 APLL is
typically configured for a frequency of 311.04MHz to get 19.44MHz and/or 38.88MHz output
clocks to distribute to system line cards.)
chosen in step 2.
frequency determined in step 3. Configure the T4FREQ field in register
Table 7-12
DPLL, the T4APT0 and T0FT4 fields in
7-12.
in the OFREQn fields of registers
DIG2F[1:0]
SETTING
IN
Table 7-9
Table 7-9
MCR7
00
10
00
01
00
01
10
11
00
01
10
11
SETTING IN
for the T4 APLL frequency determined in step 3. If the T4 APLL is locked to the T0
DIG1SS
MCR6
to select a set of output frequencies for each APLL, T0 and T4. Each APLL can
0
0
0
0
1
1
1
1
Table 7-9
and
SETTING
IN
DIG2SS
MCR6
Table
0
0
1
1
0
0
0
0
1
1
1
1
Table 7-14
the T0 and T4 APLL frequencies required for the frequency sets
7-13, configure the frequencies of output clocks OC1 through OC7
FREQUENCY
FREQUENCY
16.384
12.352
(MHz)
2.048
4.096
8.192
1.544
3.088
6.176
OCR1
10.000
19.440
38.880
16.384
12.352
(MHz)
6.312
2.048
4.096
8.192
1.544
3.088
6.176
also indicates the expected jitter amplitude for each frequency.
through
T0CR1
T0CR1
(pk-pk ns,
JITTER
OCR4
ns, typ)
JITTER
must also be configured as shown in
(pk-pk
typ)
as shown in
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
<1
and the AOFn bit in the
Table 7-10
T4CR1
for the T0 APLL
OCR5
as shown in
register.
Table
39