ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 2

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

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________________________________________________________________________________________ DS3104-SE
5.1
5.2
5.3
5.4
5.5
5.6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.8.1
7.8.2
7.9.1
STANDARDS COMPLIANCE ..........................................................................................................6
APPLICATION EXAMPLE ...............................................................................................................7
BLOCK DIAGRAM ...........................................................................................................................8
DETAILED DESCRIPTION ..............................................................................................................9
DETAILED FEATURES .................................................................................................................11
PIN DESCRIPTIONS ......................................................................................................................13
FUNCTIONAL DESCRIPTION .......................................................................................................17
I
T
L
O
O
G
O
D
L
I
I
I
DPLL A
O
F
NPUT
NPUT
NPUT
NPUT
INE
OCAL
IMING
RAME AND
EVICE
UTPUT
UTPUT
ENERAL
VERVIEW
UTPUT
Signal Format Configuration ................................................................................................................ 19
Frequency Configuration...................................................................................................................... 20
Frequency Monitoring .......................................................................................................................... 21
Activity Monitoring ................................................................................................................................ 21
Selected Reference Activity Monitoring ............................................................................................... 21
Priority Configuration............................................................................................................................ 22
Automatic Selection Algorithm ............................................................................................................. 22
Forced Selection .................................................................................................................................. 23
Ultra-Fast Reference Switching ........................................................................................................... 23
External Reference Switching Mode.................................................................................................... 24
Output Clock Phase Continuity During Reference Switching .............................................................. 24
T0 DPLL State Machine ....................................................................................................................... 26
T4 DPLL State Machine ....................................................................................................................... 29
Bandwidth ............................................................................................................................................ 31
Damping Factor.................................................................................................................................... 31
Phase Detectors................................................................................................................................... 31
Loss of Phase Lock Detection ............................................................................................................. 32
Phase Build-Out ................................................................................................................................... 33
Input to Output (Manual) Phase Adjustment........................................................................................ 33
Phase Recalibration ............................................................................................................................. 33
Frequency and Phase Measurement................................................................................................... 34
Input Jitter Tolerance ........................................................................................................................... 35
Jitter and Wander Transfer .................................................................................................................. 35
Output Jitter and Wander ..................................................................................................................... 36
Signal Format Configuration ................................................................................................................ 37
Frequency Configuration...................................................................................................................... 37
Sampling .............................................................................................................................................. 45
C
C
C
C
C
ARD TO
O
C
I
LOCK
LOCK
LOCK
LOCK
RCHITECTURE AND
DENTIFICATION AND
APLL F
C
C
SCILLATOR AND
ARD TO
F
LOCK
LOCK
....................................................................................................................................17
EATURES
M
F
C
M
P
ULTIFRAME
T
EATURES
RIORITY
ONFIGURATION
ONITORING
IMING
F
C
EATURES
L
EATURES
ONFIGURATION
INE
.....................................................................................................................12
C
C
, S
ARD
ARD
M
...............................................................................................................11
A
.............................................................................................................12
ELECTION AND
ASTER
............................................................................................................12
............................................................................................................21
C
LIGNMENT
DPLL F
DPLL F
P
ONFIGURATION
ROTECTION
......................................................................................................19
...................................................................................................37
C
LOCK
EATURES
EATURES
............................................................................................45
S
C
.....................................................................................18
WITCHING
ONFIGURATION
..................................................................................25
(T0 DPLL)..............................................................11
(T4 DPLL)..............................................................11
.....................................................................22
.............................................................18
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