ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 80

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 6: Output Clock 5 Signal Format (OC5SF[1:0]). See Section 7.8.1.
Bits 5 to 4: Output Clock 4 Signal Format (OC4SF[1:0]). See Section 7.8.1.
Bits 3 to 2: Output Clock 7 Signal Format (OC7SF[1:0]). See Section 7.8.1.
Bits 1 to 0: Output Clock 6 Signal Format (OC6SF[1:0]). See Section 7.8.1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7.3.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen)
when the DPLL reaches minimum or maximum frequency, as set by the HARDLIM field in
When the integral path is frozen, the current DPLL frequency in registers FREQ1,
frozen. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. See Section 7.7.3.
________________________________________________________________________________________ DS3104-SE
00 = Output disabled (default)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible
11 = 3V LVDS compatible
00 = Output disabled (default)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible
11 = 3V LVDS compatible
00 = Output disabled (default)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible
11 = 3V LVDS compatible
00 = Output disabled (default)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible
11 = 3V LVDS compatible
0 = Always selects locked bandwidth from the
1 = Automatically selects either locked bandwidth
0 = Do not freeze integral path at min/max frequency
1 = Freeze integral path at min/max frequency
register) as appropriate
AUTOBW
Bit 7
Bit 7
0
1
OC5SF[1:0]
Bit 6
Bit 6
—
0
1
MCR8
Master Configuration Register 8
3Ah
MCR9
Master Configuration Register 9
3Bh
Bit 5
Bit 5
—
0
1
OC4SF[1:0]
T0LBW
Bit 4
Bit 4
—
0
1
(T0LBW
register
LIMINT
register) or acquisition bandwidth
Bit 3
Bit 3
0
1
OC7SF[1:0]
Bit 2
Bit 2
—
0
0
FREQ2
DLIMIT1
Bit 1
Bit 1
—
and
0
1
OC6SF[1:0]
FREQ3
(T0ABW
and DLIMIT2.
Bit 0
Bit 0
—
0
1
is also
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