ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 128
ds3104-se
Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104-SE.pdf
(135 pages)
- Current page: 128 of 135
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10.5 JTAG Interface Timing
Table 10-11. JTAG Interface Timing
(VDD = 1.8V r10%; VDDIO = 3.3V r5%, T
Figure 10-5. JTAG Timing Diagram
________________________________________________________________________________________ DS3104-SE
JTCLK Clock Period
JTCLK Clock High/Low Time (Note 1)
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
JTCLK to JTDO High-Impedance Delay (Note 2)
JTRST Width Low Time
Note 1:
Note 2:
JTDI, JTMS, JTRST
Clock can be stopped high or low.
Not tested during production test.
JTRST
JTCLK
JTDO
PARAMETER
t6
t7
t2
A
= -40°C to +85°C.) (See
t4
SYMBOL
t2/t3
t1
t1
t4
t5
t6
t7
t8
t5
MIN
100
50
50
50
2
2
t3
t8
Figure
1000
TYP
500
10-5.)
MAX
50
50
UNITS
ns
ns
ns
ns
ns
ns
ns
128
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