ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 83
ds3104-se
Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104-SE.pdf
(135 pages)
- Current page: 83 of 135
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Interrupt Enable for Input Clock Status Change (IC8 and IC[6:1]). Each of these bits is an
interrupt enable control for the corresponding bit in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Interrupt Enable for T0 DPLL State Change (STATE). This bit is an interrupt enable for the STATE bit in
the
Bit 6: Interrupt Enable for Selected Reference Failed (SRFAIL). This bit is an interrupt enable for the SRFAIL bit
in the
Bit 0: Interrupt Enable for Input Clock Status Change (IC9). This bit is an interrupt enable control for the IC9 bit
in the
________________________________________________________________________________________ DS3104-SE
MSR2
MSR2
MSR2
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
register.
register.
register.
STATE
Bit 7
Bit 7
IC8
0
0
SRFAIL
Bit 6
Bit 6
—
0
0
IER1
Interrupt Enable Register 1
43h
IER2
Interrupt Enable Register 2
44h
Bit 5
Bit 5
IC6
—
0
0
Bit 4
Bit 4
MSR1
IC5
—
0
0
register.
Bit 3
Bit 3
IC4
—
0
0
Bit 2
Bit 2
IC3
—
0
0
Bit 1
Bit 1
IC2
—
0
0
Bit 0
Bit 0
IC1
IC9
0
0
83
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