ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 125
ds3104-se
Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104-SE.pdf
(135 pages)
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10.2 Input Clock Timing
Table 10-7. Input Clock Timing
(VDD = 1.8V r10%; VDDIO = 3.3V r5%, T
10.3 Output Clock Timing
Table 10-8. Input Clock to Output Clock Delay
Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode
See Section
________________________________________________________________________________________ DS3104-SE
Input Clock Period, CMOS/TTL Input Pins
Input Clock Period, LVDS/LVPECL Input Pins
Input Clock High, Low Time
FREQUENCY
8kHz (FSYNC)
FREQUENCY
155.52MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
44.736MHz
34.368MHz
155.52MHz
311.04MHz
6.48MHz
1.544MHz
2.048MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
OUTPUT
6.48MHz
INPUT
8kHz
2kHz
8kHz
7.9
for details on frame sync alignment and the SYNC[1:3] pins.
PARAMETER
FREQUENCY
155.52MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
OUTPUT CLOCK FALLING EDGE (ns)
OUTPUT
DELAY, MFSYNC FALLING EDGE TO
6.48MHz
8kHz
-2.0 r 1.25ns
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
-2.0 r 1.25
0.0 r 1.25
0.0 r 1.25
0.0 r 0.5
0.0 r 0.5
0.0 r 0.5
DELAY, INPUT CLOCK
A
EDGE TO OUTPUT
CLOCK EDGE (ns)
= -40°C to +85°C)
SYMBOL
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
0.0 r 1.5
t
t
t
H
CYC
CYC
, t
L
whichever is smaller
6.4ns (156.25MHz)
3ns or 30% of t
8ns (125MHz)
MIN
CYC
,
TYP
500Ps (2kHz)
500Ps (2kHz)
MAX
125
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