ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 114

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Phase Offset Recalibration (RECAL). When set to 1 this configuration bit causes a recalibration of the
phase offset between the output clocks and the selected reference. This process puts the DPLL into mini holdover,
internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET
the RECAL process causes no change in the phase offset of the output clocks. RECAL is automatically reset to 0
when recalibration is complete. See Section 7.7.8.
Bits 6 to 4: Sync Monitor Limit (MONLIM[2:0]). This field configures the sync monitor limit. When the external
frame sync input is misaligned with respect to the MFSYNC output by the specified number of resampling clock
cycles then a frame sync monitor alarm is declared in the FSMON bit of the
Bits 3 to 0: Sync Reference Source (SOURCE[3:0]). There are two modes of external frame sync operation, a
mode using a single input pin (SYNC1) and a mode using three input pins (SYNC1, SYNC2, and SYNC3).
When SOURCE = 11XX one of The SYNC1, SYNC2, and SYNC3 pins is selected as the external sync reference
depending on which input clock is selected for T0. See Section 7.9.7.
When SOURCE! = 11XX and automatic external frame sync is enabled (AEFSEN = 1 in the
external sync reference on the SYNC1 pin is enabled when the T0 DPLL is locked to the input clock specified by
the SOURCE field. See Section 7.9.
________________________________________________________________________________________ DS3104-SE
0 = Normal operation
1 = Phase offset recalibration
000 = r 1UI
001 = r 2UI
010 = r 3UI
011 = r 4UI
100 = r 5UI
101 = r 6UI
110 = r 7UI
111 = r 8UI
0000 = {unused value, undefined}
0001 = IC1
0010 = IC2
0011 = IC3
0100 = IC4
0101 = IC5
0110 = IC6
0111 = {unused value, undefined}
1000 = IC8
1001 = IC9
1010 to 1011 = {unused value, undefined}
11XX = SYNC1, SYNC2, and SYNC3 enabled (see Section 7.9.7)
registers, and then switches the DPLL out of mini holdover. Unlike simply writing the
RECAL
Bit 7
0
Bit 6
0
FSCR3
Frame Sync Configuration Register 3
7Ch
MONLIM[2:0]
Bit 5
1
Bit 4
0
Bit 3
1
OPSTATE
Bit 2
SOURCE[3:0]
0
register. See Section 7.9.6.
Bit 1
MCR3
1
OFFSET
register), the
registers,
Bit 0
1
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