ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 85
ds3104-se
Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104-SE.pdf
(135 pages)
- Current page: 85 of 135
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field
contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The
frequency is divided by DIVN[15:0] + 1. See Section 7.4.2.4.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the
________________________________________________________________________________________ DS3104-SE
Bit 7
Bit 7
1
0
Bit 6
Bit 6
1
0
DIVN1
DIVN Register 1
46h
DIVN2
DIVN Register 2
47h
Bit 5
Bit 5
1
1
DIVN1
Bit 4
Bit 4
register description.
1
1
DIVN[15:8]
DIVN[7:0]
Bit 3
Bit 3
1
1
Bit 2
Bit 2
1
1
Bit 1
Bit 1
1
1
Bit 0
Bit 0
1
1
85
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