ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 36
ds3104-se
Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104-SE.pdf
(135 pages)
- Current page: 36 of 135
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7.7.13 Output Jitter and Wander
Several factors contribute to jitter and wander on the output clocks, including:
The DPLL in the device has programmable bandwidth (see Section 7.7.3). With respect to jitter and wander, the
DPLL behaves as a low-pass filter with a programmable pole. The bandwidth of the DPLL is normally set low
enough to strongly attenuate jitter. The wander and jitter attenuation depends on the DPLL bandwidth chosen.
Over time frequency changes in the local oscillator can cause a phase difference between the selected reference
and the output clocks. This is especially true at lower frequency DPLL bandwidths because the DPLL’s rate of
change may be slower than the oscillator’s rate of change. Oscillators with better stability will minimize this effect.
In the most demanding applications an OCXO may be required rather than a TCXO.
________________________________________________________________________________________ DS3104-SE
x
x
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Jitter and wander amplitude on the selected reference (while in the locked state)
The jitter/wander transfer characteristic of the device (while in the locked state)
The jitter and wander on the local oscillator clock signal (especially wander while in the
holdover state)
36
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