ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 72

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Device Reset (RST). When this bit is high the entire device is held in reset, and all register fields, except the
RST bit itself, are reset to their default states. When RST is active, the register fields with pin-programmed defaults
do not latch their values from the corresponding input pins. Instead these fields are reset to the default values that
were latched from the pins when the RST pin was last active. See Section 7.11.
Bit 5: Frequency Range Detect Enable (FREN). When this bit is high the frequency of each input clock is
measured and used to quickly declare the input inactive.
Bit 4: T0 DPLL LOCK Pin Enable (LOCKPIN). When this bit is high the LOCK pin indicates when the T0 DPLL
state machine is in the LOCK state (OPSTATE.T0STATE = 100).
Bits 2 to 0: T0 DPLL State Control (T0STATE[2:0]). This field allows the T0 DPLL state machine to be forced to
a specified state. The state machine will remain in the forced state, and therefore cannot react to alarms and other
events, as long as T0STATE is not equal to 000. See Section 7.7.1.
________________________________________________________________________________________ DS3104-SE
0 = Normal operation
1 = Reset
0 = Frequency Range Detect disabled
1 = Frequency Range Detect enabled
0 = LOCK pin is not driven
1 = LOCK pin is driven high when the T0 DPLL is in the Lock state
000 = Automatic (normal state machine operation)
001 = Free-run
010 = Holdover
011 = {unused value}
100 = Locked
101 = Prelocked 2
110 = Prelocked
111 = Loss-of-lock
Bit 7
RST
0
Bit 6
—
0
MCR1
Master Configuration Register 1
32h
FREN
Bit 5
1
LOCKPIN
Bit 4
0
Bit 3
—
0
Bit 2
0
T0STATE[2:0]
Bit 1
0
Bit 0
0
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