mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 19

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Table 11:
PDF: 09005aef82ea3742/Source: 09005aef82ea371a
512mb_mobile_sdram_y47m__2.fm - Rev. B 4/08 EN
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
AC Functional Characteristics
Notes 1–5 apply to all parameters
Notes:
10. Auto precharge mode only. The precharge timing budget (
11. CLK must be toggled a minimum of two times during this period.
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper operation
3. In addition to meeting the transition rate specification, the clock and CKE must transit
4. Outputs measured for 1.8V at 0.9V with equivalent load:
5. AC timing tests have V
6. The clock frequency must remain constant (stable clock is defined as a signal cycling within
7.
8. The 512Mb Mobile SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (
9. AC characteristics assume
over the full temperature range (0°C ≤ T
–40°C ≤ T
between V
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
input transition time is longer than
and V
timing constraints specified for the clock ball) during access or precharge states (READ,
WRITE, including
rate.
t
erence to V
ing a distributed AUTO REFRESH command every 7.8125µs meets the refresh requirement
and ensures that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can
be issued in a burst at the minimum cycle rate (
the first clock delay and after the last WRITE is executed. May not exceed the limit set for
precharge mode.
Q
HZ defines the time at which the output achieves the open circuit condition, it is not a ref-
IH
(MIN) and no longer at the V
A
≤ +85°C industrial temperature) is ensured.
IH
OH
and V
or V
20pF
t
WR, and PRECHARGE commands). CKE may be used to reduce the data
OL
IL
. The last valid data element will meet
(or between V
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
IL
and Vih with timing referenced to V
t
T = 1ns.
19
CL = 3
CL = 2
IL
t
T (MAX), then the timing is referenced at V
and V
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/2 crossover point.
A
≤ +70°C standard temperature and
Symbol
IH
t
t
t
t
t
t
t
t
CKED
t
) in a monotonic manner.
t
t
t
DQM
DWD
t
t
MRD
DQD
ROH
DQZ
CCD
DAL
BDL
CDL
DPL
PED
RDL
t
RFC), once every 64ms.
-75
Electrical Specifications
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
t
RP) begins at x ns for -75 after
t
OH before going High-Z.
IH
/2 = crossover point. If the
©2007 Micron Technology, Inc. All rights reserved.
-8
2
1
1
1
1
5
2
0
0
2
0
2
1
2
3
Units
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REF). Provid-
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
IL
(MAX)
Notes
14, 16
15, 16
15, 16
12
12
13
13
12
12
12
12
13
12