mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 39

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

CAS Latency (CL)
Figure 15:
Operating Mode
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
CAS Latency
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
is valid by clock edge n + m. For example, assuming that the clock cycle time is such that
all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs start driving after T1 and the data is valid by T2, as
shown in Figure 15.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
Command
Command
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
39
t
t AC
LZ
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
Don’t Care
Undefined
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
T4
Operations