mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 37

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Register Definition
Mode Register
Figure 14:
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
Mn+2 Mn+1
0
0
1
1
Mode Register Definition
0
1
0
1
Mn+2
n+2 n+1
0
Mode Register Definition
Base mode register
Reserved
Extended mode register
Reserved
BA1
M9
0
1
There are two mode registers in the Mobile SDRAM component, the mode register and
the extended mode register (EMR). The mode register is illustrated in Figure 14 on
page 37. The mode register defines the specific mode of operation of the Mobile SDRAM,
including burst length (BL), burst type, CAS latency (CL), operating mode, and write
burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and retains the stored information until it is programmed again or the device
loses power.
Mode register bits M0–M2 specify the BL, M3 specifies the type of burst, M4–M6 specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 through Mn should be set to zero to ensure compatibility with future revisions.
Mn + 1and Mn + 2 should be set to zero to prevent the extended mode register from
being programmed.
The mode registers must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
Mn+1
MRD before initiating the subsequent operation. Violating either of these requirements
0
BA0
Programmed burst length
M8
0
Single location access
–
Write Burst Mode
Mn
An
n
Reserved*
M7
0
–
...
...
...
Normal operation
All other states reserved
Operating Mode
10
A10
M10
WB
M6
0
0
0
0
1
1
1
1
A9
M9
9
Op mode
M5
0
0
1
1
0
0
1
1
A8
M8
8
M4
0
1
0
1
0
1
0
1
A7
M7
7
CAS latency
37
A6
M6
6
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
A5
M5
2
3
4
A4
M4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BT
A3
M3
3
M2
Burst length
0
0
0
0
1
1
1
1
M2
2
A2
M1
0
0
1
1
0
0
1
1
M1
1
A1
* Should be programmed
M0
M3
0
1
0
1
0
1
0
1
0
1
to “0” to ensure compatibility
with future devices.
A0
M0
0
Continuous
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
Address bus
1
2
4
8
Mode
register (Mx)
Burst Length
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
Operations