mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 41

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Temperature-Compensated Self Refresh (TCSR)
Partial-Array Self Refresh (PASR)
Output Drive Strength
Bank/Row Activation
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
1. All banks (banks 0, 1, 2, and 3)
2. Two banks (banks 0 and 1; BA1= 0)
3. One bank (bank 0; BA1 = BA0 = 0)
4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0)
5. Quarter bank (bank 0; BA1 = BA0 = row address MSB - 1 = 0)
Micron Mobile SDRAM includes a temperature sensor that is implemented for auto-
matic control of the self refresh oscillator on the device. Therefore, it is recommended
that the TCSR control bits in the EMR not be programmed or used. Programming the
TCSR bits has no effect on the device. The self refresh oscillator will continue refresh at
the optimal factory programmed rate for the device temperature.
For further power savings during self refresh, the PASR feature enables the controller to
select the amount of memory that is refreshed during self refresh. The following refresh
options are available:
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks or segments of a bank in PASR are refreshed during self refresh. It
is important to note that data in unused banks or portions of banks is lost when PASR is
used.
Because the Mobile DDR SDRAM is designed for use in smaller systems that are typically
point-to-point connections, an option to control the drive strength of the output buffers
is provided. Drive strength should be selected based on the expected loading of the
memory bus. There are four supported settings for the output drivers: 25Ω, 37Ω, 55Ω,
and 80Ω internal impedance. These are full, three-quarter, one-half, and one-quarter
drive strengths, respectively.
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, that
selects both the bank and the row to be activated (see Figure 17 on page 42).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 17 on page 42, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
41
t
t
CK ≤ 3. (The same procedure is used to convert other
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) should be divided by
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
Operations
t
RC.