mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 40

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Write Burst Mode
Extended Mode Register (EMR)
Figure 16:
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
En + 2
0
0
1
1
En + 1
Extended Mode Register
0
1
0
1
En
0
–
Notes:
Mode Register Definition
Standard mode register
Reserved
Extended mode register
Reserved
...
0
–
E10
0
–
E9
When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
The EMR controls the functions beyond those controlled by the mode register. These
additional functions are special features of the mobile device that helps reduce overall
system power consumption. They include temperature-compensated self refresh
(TCSR) control, partial-array self refresh (PASR), and output drive strength.
The EMR is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and
retains the stored information until it is programmed again or the device loses power.
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The EMR must be programmed with E7–En set to “0.” It must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time
before initiating any subsequent operation. Violating either of these requirements
results in unspecified operation. After the values are entered, the EMR settings are
retained even after exiting deep power-down mode.
0
–
n+2
1
BA1
E8
0
–
n+1
0
BA0
E7–E0
Valid
–
A
n
...
Normal Operation
All other states reserved
Operation
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
0
0
0
0
1
1
1
1
E6
0
0
1
1
0
0
1
1
9
E5
0
1
0
1
0
1
0
1
8
40
7
DS
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
Partial-Array Self Refresh Coverage
Full array
Half array
Quarter array
Reserved
Reserved
One-eighth array
One-sixteenth array
Reserved
PASR
1
0
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
Address bus
Extended mode
register (Ex)
Operations