mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 30

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 12:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1Gb_DDR2_x4x8x16_D2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Parameter/Condition
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating; Data
bus inputs are floating
Operating bank interleave read current: All bank
interleaving reads, I
AL =
t
is HIGH, CS# is HIGH between valid commands; Address
bus inputs are stable during deselects; Data bus inputs
are switching; See “Idd7 Conditions” on page 26 for
details
RC =
t
RCD (I
t
RC (I
DD
DD
),
DDR2 I
Notes: 1–7 (page 30) apply to the entire table
) - 1 ×
t
RRD =
Notes:
OUT
t
CK (I
DD
t
RRD (I
= 0mA; BL = 4, CL = CL (I
Specifications and Conditions (Die Revision E and G) (continued)
DD
1. I
2. Input slew rate is specified by AC parametric test conditions (Table 9 on page 25).
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
5. Definitions for I
6. I
7. The following I
);
DD
t
CK =
V
I
LOW
HIGH
Stable
Floating
Switching
Switching
when operated outside of the range 0°C ≤ T
When
T
When
T
),
DD
DD
DD
DD
C
C
DD
t
≤ 0°C
≥ 85°C
RCD =
1, I
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
values must be met with all combinations of EMR bits 10 and 11.
= +1.8V ±0.1V, V
t
CK (I
DD
4R, and I
t
RCD (I
DD
I
derated by 2 percent; and I
I
derated by 2 percent; I
derated by 30 percent; and I
increase by this amount if T
),
DD
DD
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
IN
IN
DD
2P and I
0, I
DD
DD
≤ V
DD
≥ V
DD
s must be derated (I
DD
); CKE
conditions:
),
7 require A12 in EMR to be enabled during testing.
IL
IH
DD
1, I
(
(
AC
AC
Q = +1.8V ±0.1V, V
DD
REF
DD
) MAX
) MIN
3P (slow) must be derated by 4 percent; I
2N, I
Symbol Configuration -187E
= V
I
30
I
DD
I
DD
DD
DD
DD
6L
6
7
Q/2
2Q, I
Electrical Specifications – I
DD
DD
2P must be derated by 20 percent; I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
x4, x8, x16
DD
C
limits increase) on IT-option and AT-option devices
3N, I
DD
x4, x8
< 85°C and the 2X refresh option is still enabled)
DD
6 and I
x16
6 must be derated by 80 percent (I
C
L = +1.8V ±0.1V, V
DD
≤ 85°C:
3P (fast), I
DD
1Gb: x4, x8, x16 DDR2 SDRAM
7 must be derated by 7 percent
425
520
7
5
DD
4R, I
-25E/
335
440
-25
REF
7
5
©2004 Micron Technology, Inc. All rights reserved.
DD
= V
DD
4W, and I
-3E/
4R and I
280
350
DD
-3
7
5
DD
Q/2.
DD
C
-37E -5E Units
270 260
330 300
3Pslow must be
Parameters
≤ +85°C.
7
5
DD
DD
DD
5W must be
5W must be
6 will
7
5
mA
mA