mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 87

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

READ
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
READ bursts are initiated with a READ command. The starting column and bank
addresses are provided with the READ command, and auto precharge is either enabled
or disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address will
be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL:
RL = AL + CL. The value for AL and CL are programmable via the MR and EMR
commands, respectively. Each subsequent data-out element will be valid nominally at
the next positive or negative clock edge (at the next crossing of CK and CK#). Figure 47
on page 88 shows examples of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state
on DQS and the HIGH state on DQS# are known as the read preamble (
state on DQS and the HIGH state on DQS# coincident with the last data-out element are
known as the read postamble (
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of
window hold), and the valid data window are depicted in Figure 56 on page 95 and
Figure 57 on page 96. A detailed explanation of
t
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 48
on page 89).
Nonconsecutive read data is illustrated in Figure 49 on page 90. Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing (see Table 43 on page 93).
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to
complete the entire READ burst. However, a READ (with auto precharge disabled) using
BL = 8 operation may be interrupted and truncated only by another READ burst as long
as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. As shown in Figure 50 on page 90, READ burst BL = 8 operations may not
be interrupted or truncated with any other command except another READ command.
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 51 on
page 91. The
Figure 59 on page 99.)
AC (data-out transition skew to CK) is shown in Figure 58 on page 97.
t
DQSS (NOM) case is shown (
87
t
RPST).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ (valid data-out skew),
t
DQSS [MIN] and
t
DQSCK (DQS transition skew to CK) and
1Gb: x4, x8, x16 DDR2 SDRAM
t
DQSS [MAX] are defined in
©2003 Micron Technology, Inc. All rights reserved.
t
t
RPRE). The LOW
QH (data-out
Operations