mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 81

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 40:
DLL Enable/Disable
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Extended Mode Register Definition
Notes:
1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro-
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed on page 74, during initialization of the ODC operation, all three bits must be set
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 40. The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically reenabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before
a READ command can be issued to allow time for the internal clock to synchronize with
the external clock. Failing to wait for synchronization to occur may result in a violation
of the
BA2
E15
16
0
0
0
1
1
grammed to “0.”
for future use and must be programmed to “0.”
to “1” for the OCD default state, then set to “0” before initialization is finished.
1
E14
BA1
15
MRS
0
1
0
1
t
E12
AC or
0
1
BA0
14
E9
Extended mode register (EMR2)
Extended mode register (EMR3)
0
0
0
1
1
E11
Extended mode register (EMR)
0
1
Disabled
Outputs
Enabled
0
E8
An
n
RDQS Enable
0
0
1
0
1
E10
Mode register (MR)
0
1
Out
Mode Register Set
2
t
E7
12
0
1
0
0
1
DQSCK parameters.
A12 A11
No
Yes
DQS# Enable
RDQS
Disable
Enable
OCD Operation
OCD exit
Reserved
Reserved
Reserved
Enable OCD defaults
11
DQS#
10
A10
OCD Program
9
A9
E6
0
0
1
1
8
A8
E2
0
1
0
1
7
A7 A6 A5 A4 A3
R
81
R
TT
R
TT
TT
6
(Nominal)
150Ω
disabled
75Ω
50Ω
Posted CAS# R
5
E5
0
0
0
0
1
1
1
1
4
E4
0
0
1
1
0
0
1
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
E3
0
1
0
1
0
1
0
1
TT
2
Posted CAS# Additive Latency (AL)
A2 A1 A0
ODS
E1
0
1
1
DLL
E0
0
1
Output Drive Strength
0
1Gb: x4, x8, x16 DDR2 SDRAM
Reserved
Disable (test/debug)
Enable (normal)
Address bus
Extended mode
register (Ex)
Reduced
0
1
2
3
4
5
6
DLL Enable
Full
©2003 Micron Technology, Inc. All rights reserved.
Operations